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TLV320AIC12K MSB Bit toggling without any input

Hi,

  On MSB bit of DOUT I see this bit toggling frequently. I get values like:

  0x0023, 0x0025, 0x8020, 0x8023 and so on. 0x80xx is a large -ve value in 2's complement. And I get lot of noise. 

FS D15 D14 .... D0 .................................. FS D15 D14 .... D0

Pl. advise how to remove the MSB bit toggling. 

REgards,

Hari

My configuration is 

/* Control 1 */
#define CTRL1_INIT (CTRL1_CX | CTRL1_DAC16)

/* Control 2 */
#define CTRL2_INIT (CTRL2_TURBO | CTRL2_HPC_I2C | CTRL2_I2C_ADR(4))

/* Control 3 */
#define CTRL3_INIT (CTRL3_PWDN_ON | CTRL3_OSR_128 | CTRL3_ASRF_1)

/* Control 5A */

#define CTRL5A_REG 5
#define CTRL5A_INIT (GAIN_11db | CTRL5A_SUBREG) // ADC Gain

/* Control 5B */
#define CTRL5B_INIT (GAIN_0db | CTRL5B_SUBREG) // DAC Gain

/* Control 5C */
#define CTRL5C_REG 5
#define CTRL5C_INIT (CTRL5C_SIDE_GAIN_MUTE | CTRL5C_IN_GAIN_6db | CTRL5C_SUBREG) // Buffer Gain

/* Control 5D */
#define CTRL5D_INIT (CTRL5D_SUBREG)

/* Control 6 */
#define CTRL6_INIT (CTRL6_PSD0_SINGLE_END | CTRL6_AINSEL_M1)

/* CODEC i2c base address */
#define CODEC_I2C_ADR 0x40

Some more information on the design:

     - 8MHz is the TDM clock

   - 8KHz is the Frame Sync

  INP1 is input

   

  • Hi, Hari,

    I have asked my colleague to look at your request. He should get back to you early next week.

    -d2

  • 6332.Guidelines for configuring the AIC1x.pdf

    Hi,

      Now I follwed a note on "Guidelines for configuring the AIC1x". Can anyone explain the reason behind this and do I foresee any more problems? 

    Regards,

    Hari

    Earlier I had a sequence:

    Non-Working Sequence (with MSB bit toggling)

    REG_INIT codec_init[] = {
    { CTRL1_REG, CTRL1_INIT },    <---------------------- This Register Init was causing the problem of MSB bit toggling. 
    { CTRL2_REG, CTRL2_INIT },
    { CTRL3_REG, CTRL3_INIT },
    { CTRL4_REG, CTRL4_FSDIV_PN | 0 | 4 << 3 }, 
    { CTRL4_REG, CTRL4_FSDIV_M | 2 }, 
    { CTRL5A_REG, CTRL5A_INIT },
    { CTRL5B_REG, CTRL5B_INIT },
    { CTRL5C_REG, CTRL5C_INIT },
    { CTRL5D_REG, CTRL5D_INIT },
    { CTRL6_REG, CTRL6_INIT },
    { CTRL1_REG, CTRL1_INIT },
    { 0xff, 0x00 }
    }

    Working Sequence (with MSB bit toggling)

    REG_INIT codec_init[] = {
    { CTRL2_REG, CTRL2_INIT },
    { CTRL3_REG, CTRL3_INIT },
    { CTRL4_REG, CTRL4_FSDIV_PN | 0 | 4 << 3 }, 
    { CTRL4_REG, CTRL4_FSDIV_M | 2 }, 
    { CTRL5A_REG, CTRL5A_INIT },
    { CTRL5B_REG, CTRL5B_INIT },
    { CTRL5C_REG, CTRL5C_INIT },
    { CTRL5D_REG, CTRL5D_INIT },
    { CTRL6_REG, CTRL6_INIT },
    { CTRL1_REG, CTRL1_INIT },
    { 0xff, 0x00 }
    }