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TLV320AIC3204 clock calculation help please

Hello,

I have an MCLK of 24.576MHz and my microcontroller is also providing the CODEC with a 128kHz 50% duty BCLK. In return, I am getting a 16kHz WCLK from the CODEC where the high-period is for the left channel and the low period is for the right channel. This is perfect for 8kHz-8bit PCM mono.

Now, I want to increase the sampling rate to 11.025kHz and maybe 22.050kHz. I could use 16-bit samples and manage the data so I can send either 8 or 16 bit samples. ***NOTE: I am *only* using the ADC, not the DAC.

Also, I have the ability to change the BCLK to anything up to (I believe) 2.048MHz 50% duty.

I made myself a spreadsheet where I can plug-in any values (same as with the AIC3204 application, but all on one page) and it will provide me with the ADC_FS.

But I just can't get what I need.... so can anyone please tell me how in the world can I find the right numbers (using the PLL) to obtain an ADC_FS of 11.025 and 22.050 kHz given that my MCLK is 24.576MHz??

I've tried so many different combinations and I just cannot reach the perfect round value of 11.025kHz... I always have some decimals and obviously that won't work.

Thank you!

Benoit 

  • Hi, Benoit,

    I believe the GUI for the AIC3204 EVM has a PLL calculator in it. You can find the GUI here.

    -d2

  • Hi Don,

    Sorry, I should have mentioned that I *do* have the AIC3204 software but I just cannot figure-out how to adjust the parameters to get 11.025kHz and 22.050kHz out of a 24.576MHz OR 38.4MHz clock.

    But first, let me backup here and explain the reason I am mentioning two clock frequencies:

    First: the PIC microcontroller doing the audio streaming is mounted on one development board mounted with a 38.4MHz crystal. The reason I use this precise frequency is because it is the highest frequency I can use that is the closest to 40MHz that will let me output a 128kHz PWM. Anything in-between 38.4MHz and 40MHz will not let me output a 128kHz PWM. That 128kHz PWM is used for generating the BCLK signal in order to get 64kbps audio out of the CODEC. And the reason I use that frequency is because I cannot go above 40MHz therefore 38.4 is the closest to 40MHz frequency I can use *and* is the fastest that will let me get a 128kHz PWM.

    Second: the reason I am trying to calculate 11kHz and 22kHz using the 24.576MHz frequency is because the CODEC is mounted on a second development board AND that frequency comes from a powered oscillator mounted on a *third* development board. Yes, this sounds like a big spaghetti mess but everything is currently working perfectly fine @ 64kbps (8-bit audio, mono, 8kHz sampling).

    Third: the reason I want the PLL, NADC, MADC and AOSR parameters calculated using the 38.4MHz and 24.576MHz frequencies is that for my *current* spaghetti setup, I have to use the 24.576MHz crystal because the 38.4MHz is not available for the CODEC at the moment. However, when I have the single PCB fabricated, I will have a single clock source for both the CODEC and microcontroller which hopefully will be 38.4MHz.

    So getting back to my dilemma, using the AIC3204 application, I just cannot figure-out the proper calculations, regardless if I activate the PLL or not, in order to get the right R, J, D, P, NADC, MADC and AOSR values for the above-mentioned crystals of 24.576MHz and 38.4MHz.

    I hope this is clearer and I hope you now understand and perhaps shed some light. Another of your colleagues had posted an answer on a previous post giving me some R J D P values but he used values that are out of range therefore I'm back to square one.

    Thanks again,

    Benoit

  • Hello,

    I am somewhat struggling here trying to find a common clock frequency for different types of sampling rates. All I need is 8kHz, 11.025kHz and 22.050 kHz sampling rates and I only need the ADC, not the DAC.

    Since I have complete control over the CODEC for the register configurations, that clock can go straight to MCLK for 8kHz and perhaps re-routed through the PLL for the odd frequencies.

    I am using the AIC3204 CS application and trying different calculations and I just cannot seem to find the right frequency that will do all these three sampling rates, regardless if I go through the PLL or not.

    So, can anyone please help with the *exact* R, J.D, P, NADC, MADC and AOSR values along with what oscillator frequency was used to find these values?

    Thanks,

    Benoit

  • Hi, Benoit,

    I merged your recent post with your older thread as they seem interrelated. 

    I have also asked my colleague who has more experience with these issues to chime in.

    -d2

  • Ok, but in the meantime, I believe that I may have found an oscillator that will do both the PIC microcontroller and the CODEC: 36.864MHz.

    First, for the PIC microcontroller, this frequency is slightly below the 38.4MHz I needed but this frequency will be able to provide a 128kHz BCLK signal to the CODEC. So that's solved.

    Second, with 36.864MHz, using the PLL, these are the values to configure for the given sampling frequency:

    8kHz: R=1, J=4, D=0, P=3, NADC=3, MADC=8, AOSR=256

    11.025kHz: R=1, J=5, D=5125, P=4, NADC=3, MADC=6, AOSR=256

    22.050kHz: R=1, J=5, D=5125, P=2, NADC=3, MADC=6, AOSR=128

    Note that these values "work" in the AIC3204 CS application but I don't currently have such frequency with me. I will order one, try it out and post my findings here.

    In the meantime, perhaps you (or someone else) can answer this for me: using 128kHz for the CODEC's BCLK will give me only 8 bits per samples. What's the next BCLK frequency above 128kHz to have 16 bits?

    Thanks,

    Benoit