Hello,
I have an MCLK of 24.576MHz and my microcontroller is also providing the CODEC with a 128kHz 50% duty BCLK. In return, I am getting a 16kHz WCLK from the CODEC where the high-period is for the left channel and the low period is for the right channel. This is perfect for 8kHz-8bit PCM mono.
Now, I want to increase the sampling rate to 11.025kHz and maybe 22.050kHz. I could use 16-bit samples and manage the data so I can send either 8 or 16 bit samples. ***NOTE: I am *only* using the ADC, not the DAC.
Also, I have the ability to change the BCLK to anything up to (I believe) 2.048MHz 50% duty.
I made myself a spreadsheet where I can plug-in any values (same as with the AIC3204 application, but all on one page) and it will provide me with the ADC_FS.
But I just can't get what I need.... so can anyone please tell me how in the world can I find the right numbers (using the PLL) to obtain an ADC_FS of 11.025 and 22.050 kHz given that my MCLK is 24.576MHz??
I've tried so many different combinations and I just cannot reach the perfect round value of 11.025kHz... I always have some decimals and obviously that won't work.
Thank you!
Benoit