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Confirm the role of AIC3254 function.

Kaka
Guru 24520 points

Hi community member,

Please let me confirm the following question.

[Question]

Would you please teach me the function of "Primary BCLK and Primary WCLK Power Control" (Page 0 Register 29 Bit 2)?

[Background]

In my opinion, this function will generate the BCLK and WCLK in case of using Master mode in I2S even though the codec is powered down by using the function of "Analog Block Power Control".  However when I confirmed this function by using AIC3254EVM-K, those clocks did not generate.  If possible, would you please check whether my understanding is correct?

Best regards,

Kaka

  • 0
    TI__Guru**** 189401 points

    Hi, Kaka,

    Sorry for our delay. We will look into this ASAP for you.

    -d2

  • 0
    TI__Mastermind 46195 points

    Kaka-san,

    Refer to Appendix A.1 of http://www.ti.com/litv/pdf/slaa404c for example master mode script.

    The "Analog Block Power Control" register is actually a misnomer. This register actually enables level shifters for internal digital to analog block communication. If you are using a block that needs analog (e.g. PLL) then you need to enable this functionality. It is actually better to always enable this whenever using any block in the codec to avoid confusion.

    Below is an example script. Clock assumptions are mentioned below as well.

    ###############################################
    # Software Reset
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Initialize the device through software reset
    w 30 01 01
    #
    ###############################################

    ###############################################
    # Configure Power Supplies
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Disable weak AVDD in presence of external
    # AVDD supply
    w 30 01 08
    #
    # Enable Master Analog Power Control
    w 30 02 00
    #
    # Set the input power-up time to 3.1ms (for ADC)
    w 30 47 32
    #
    # Set the REF charging time to 40ms
    w 30 7b 01
    #
    ###############################################

    ###############################################
    # Clock and Interface Settings
    # ---------------------------------------------
    # The codec receives: MCLK = 11.2896 MHz
    # and generates: BLCK = 2.8224 MHz,
    # WCLK = 44.1 kHz
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # NDAC = 1, MDAC = 2, dividers powered on
    w 30 0b 81 82
    #
    # NADC = 1, MADC = 2, dividers powered off
    w 30 12 01 02
    #
    # BCLK frequency is generated from DAC_CLK
    # and N = 4, I2S forced power-up
    w 30 1D 04 84
    #
    # Set BCLK and WCLK as outputs
    w 30 1B 0C
    #
    ###############################################

    Regards,

    J-

     

  • 0 in reply to J-
    TI__Mastermind 46195 points

    Kaka,

    There was a typo. Correction is marked in purple.

    Regards,

    J-

  • 0 in reply to J-
    TI__Mastermind 46195 points

    Kaka,

    And another typo marked in blue. I promise this is the last one :)

    Regards,

    J-

  • 0 in reply to J-
    Guru 24520 points

    Hi J,

    Thank you for your response.

    But I would like to know the role of "Primary BCLK and Primary WCLK Power Control" .

    [Question]

    Is there any way to confirm the function of  "Primary BCLK and Primary WCLK Power Control" (Page 0 Register 29 Bit 2) by using AIC3245EVM-K?

    Best regards.

    Kaka

  • 0 in reply to Kaka
    TI__Mastermind 46195 points

    Kaka,

    Yes. In motherboard (USB-MODEVM), set SW2.4 to the right and SW2.5 to the left. This will 3-state I2S from USB and allow you to test with AIC3254EVM-K.

    Regards,

    J-