I am now using PLL1707 "SCKO3" to be a clock source for my FPGA's clock source to generate sck, bclk and lrck of
PCM1798. The clock output waveform at trigger position is as figure1.
After N clock cycles, the waveform becomes figure2.
May I say that the jitter is accumulated jitter? Is my jitter measurement is correct? I compared it with the output of crystal's buffer 27Mhz output "MCKO1".
The waveform after N cycles seems the same as at trigger position. When I use "SCKO3" as my FPGA clock source, the audio output seems incorrect
with sync. issue. When I use "MCKO1" as my clock source, the audio output seems correct.
What should I do if this is the real concern to ruin my clock source? Is that layout issue or device issue?
Thank you!
Brian
