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AIC3256: Is there any suggestion to do between two image loaded?

Greg Tsai
Prodigy 230 points

Hi,

I'm trying to switch two complete image in AIC3256, the complete image(.h) is build from PPS GDE.

MCU will load specify complete image by user demand.

For prevent pop-noise, is there any suggestion to do before load new image?

Such like mute or power off, and what sequence is proper?

Thanks!

Greg

  • 0
    TI__Guru**** 189401 points

    Hi, Greg,

    Sorry for the delay in responding to your thread. I have highlighted this to one of my colleagues.

    In the future, I might suggest that you put the part number in question in the title so it's easier for us to assign them.

    -d2

  • 0
    TI__Mastermind 46195 points

    Hi Greg,

    Before loading the PPS header file, power down the output amplifiers. The AIC3256 Control Software has a sample script in the typical playback configurations window. that implements this. Below is an example.

    # Power down LOL/LOR and HPL/HPR drivers
    w 30 00 01
    w 30 09 00

    Regards,

    J-

  • 0 in reply to J-
    Prodigy 230 points

    Hi J,

    Thanks for your reply, and I'd like to confirm the implementation.

    The part of original header file build from PPS GDE as below:

    static const reg_value REG_Section_program[] = {
    // ----------------------------------------
    // Software Reset
    // ----------------------------------------
    { 0,0x00}, // Select Page 0
    { 1,0x01}, // Initialize the device through software reset
    {254,0x0a}, // Delay 10ms

    // ----------------------------------------
    // Load miniDSP code
    // ----------------------------------------
    {255,0x00}, // Jump to miniDSP_A configuration
    {255,0x01}, // Jump to miniDSP_D configuration

    // ----------------------------------------
    // Power Supply Configuration
    // ----------------------------------------
    { 0,0x01}, // Select Page 1
    { 1,0x08}, // Disable weak AVDD to DVDD connection
    { 2,0x00}, // Enable Master Analog Power Control
    { 71,0x31}, // Set the input power-up time to 3.1ms
    {123,0x05}, // REF charging time to 40ms (forced power-up)
    {254,0x28}, // Delay 40ms for REF to power up

    // ----------------------------------------
    // Clock and Interface Configuration
    // ----------------------------------------
    { 0,0x00}, // Select Page 0
    { 5,0x91}, // P=1, R=1, J=8
    { 6,0x08}, // P=1, R=1, J=8
    { 7,0x00}, // D=0000 (MSB)
    { 8,0x00}, // D=0000 (LSB)
    { 4,0x03}, // PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    { 11,0x82}, // NDAC = 2, divider powered on
    { 12,0x88}, // MDAC = 8, divider powered on
    { 13,0x00}, // DOSR = 128 (MSB)
    { 14,0x80}, // DOSR = 128 (LSB)
    { 18,0x02}, // NADC = 2, divider powered off
    { 19,0x88}, // MADC = 8, divider powered on
    { 20,0x80}, // AOSR = 128
    { 29,0x10}, // ADC to DAC Loopback

    // ----------------------------------------
    // Signal Processing Settings
    // ----------------------------------------
    { 0,0x00}, // Select Page 0
    { 60,0x00}, // Use miniDSP_D for signal processing
    { 61,0x00}, // Use miniDSP_A for signal processing
    { 15,0x03}, // IDAC = 904 (MSB)
    { 16,0x88}, // IDAC = 904 (LSB)
    { 17,0x08}, // 8x Interpolation
    { 21,0x03}, // IADC = 904 (MSB)
    { 22,0x88}, // IADC = 904 (LSB)
    { 23,0x04}, // 4x Decimation
    { 0,0x08}, // Select Page 8
    { 1,0x04}, // Enable Adaptive mode for ADC
    { 0,0x2c}, // Select Page 44
    { 1,0x84}, // Enable Adaptive mode for DAC

    // ----------------------------------------
    // Input Channel Configuration
    // ----------------------------------------
    { 0,0x01}, // Select Page 1
    // { 51,0x40}, // Mic Bias enabled, Source = Avdd, 1.25V
    { 52,0x40}, // Route IN1L to LEFT_P with 10K input impedance
    { 54,0x40}, // Route CM1L to LEFT_M with 10K input impedance
    { 55,0x40}, // Route IN1R to RIGHT_P with 10K input impedance
    { 57,0x40}, // Route CM1R to RIGHT_M with 10K input impedance
    { 59,0x00}, // Enable MicPGA_L Gain Control, 0dB
    { 60,0x00}, // Enable MicPGA_R Gain Control, 0dB
    { 0,0x00}, // Select Page 0
    { 81,0xc0}, // Power up LADC/RADC
    { 82,0x00}, // Unmute LADC/RADC

    // ----------------------------------------
    // Output Channel Configuration
    // ----------------------------------------
    { 0,0x01}, // Select Page 1
    { 20,0x25}, // De-pop: 5 time constants, 6k resistance
    { 12,0x08}, // Route LDAC to HPL
    { 13,0x08}, // Route RDAC to HPR
    { 16,0x00}, // Unmute HPL driver, 0dB Gain
    { 17,0x00}, // Unmute HPR driver, 0dB Gain
    { 0,0x00}, // Select Page 0
    { 65,0x00}, // LDAC Gain = 0dB
    { 66,0x00}, // RDAC Gain = 0dB
    { 63,0xd6}, // Power up LDAC/RDAC
    { 0,0x01}, // Select Page 1
    { 9,0x30}, // Power up HPL/HPR
    { 0,0x00}, // Select Page 0
    { 64,0x00}, // Unmute LDAC/RDAC
    };

    Should I just power down output amplifier by insert the code in the header file?:

    static const reg_value REG_Section_program[] = {
    // ----------------------------------------
    // Power down the output amplifiers
    // ----------------------------------------
    { 0,0x01}, // Select Page 0
    { 9,0x00}, //  Power down the output amplifiers

    // ----------------------------------------
    // Software Reset
    // ----------------------------------------
    { 0,0x00}, // Select Page 0
    { 1,0x01}, // Initialize the device through software reset
    {254,0x0a}, // Delay 10ms

    // ----------------------------------------
    // Load miniDSP code
    // ----------------------------------------
    {255,0x00}, // Jump to miniDSP_A configuration
    {255,0x01}, // Jump to miniDSP_D configuration

    // ----------------------------------------
    // Power Supply Configuration
    // ----------------------------------------
    { 0,0x01}, // Select Page 1
    { 1,0x08}, // Disable weak AVDD to DVDD connection
    { 2,0x00}, // Enable Master Analog Power Control
    { 71,0x31}, // Set the input power-up time to 3.1ms
    {123,0x05}, // REF charging time to 40ms (forced power-up)
    {254,0x28}, // Delay 40ms for REF to power up

    // ----------------------------------------
    // Clock and Interface Configuration
    // ----------------------------------------
    { 0,0x00}, // Select Page 0
    { 5,0x91}, // P=1, R=1, J=8
    { 6,0x08}, // P=1, R=1, J=8
    { 7,0x00}, // D=0000 (MSB)
    { 8,0x00}, // D=0000 (LSB)
    { 4,0x03}, // PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    { 11,0x82}, // NDAC = 2, divider powered on
    { 12,0x88}, // MDAC = 8, divider powered on
    { 13,0x00}, // DOSR = 128 (MSB)
    { 14,0x80}, // DOSR = 128 (LSB)
    { 18,0x02}, // NADC = 2, divider powered off
    { 19,0x88}, // MADC = 8, divider powered on
    { 20,0x80}, // AOSR = 128
    { 29,0x10}, // ADC to DAC Loopback

    // ----------------------------------------
    // Signal Processing Settings
    // ----------------------------------------
    { 0,0x00}, // Select Page 0
    { 60,0x00}, // Use miniDSP_D for signal processing
    { 61,0x00}, // Use miniDSP_A for signal processing
    { 15,0x03}, // IDAC = 904 (MSB)
    { 16,0x88}, // IDAC = 904 (LSB)
    { 17,0x08}, // 8x Interpolation
    { 21,0x03}, // IADC = 904 (MSB)
    { 22,0x88}, // IADC = 904 (LSB)
    { 23,0x04}, // 4x Decimation
    { 0,0x08}, // Select Page 8
    { 1,0x04}, // Enable Adaptive mode for ADC
    { 0,0x2c}, // Select Page 44
    { 1,0x84}, // Enable Adaptive mode for DAC

    // ----------------------------------------
    // Input Channel Configuration
    // ----------------------------------------
    { 0,0x01}, // Select Page 1
    // { 51,0x40}, // Mic Bias enabled, Source = Avdd, 1.25V
    { 52,0x40}, // Route IN1L to LEFT_P with 10K input impedance
    { 54,0x40}, // Route CM1L to LEFT_M with 10K input impedance
    { 55,0x40}, // Route IN1R to RIGHT_P with 10K input impedance
    { 57,0x40}, // Route CM1R to RIGHT_M with 10K input impedance
    { 59,0x00}, // Enable MicPGA_L Gain Control, 0dB
    { 60,0x00}, // Enable MicPGA_R Gain Control, 0dB
    { 0,0x00}, // Select Page 0
    { 81,0xc0}, // Power up LADC/RADC
    { 82,0x00}, // Unmute LADC/RADC

    // ----------------------------------------
    // Output Channel Configuration
    // ----------------------------------------
    { 0,0x01}, // Select Page 1
    { 20,0x25}, // De-pop: 5 time constants, 6k resistance
    { 12,0x08}, // Route LDAC to HPL
    { 13,0x08}, // Route RDAC to HPR
    { 16,0x00}, // Unmute HPL driver, 0dB Gain
    { 17,0x00}, // Unmute HPR driver, 0dB Gain
    { 0,0x00}, // Select Page 0
    { 65,0x00}, // LDAC Gain = 0dB
    { 66,0x00}, // RDAC Gain = 0dB
    { 63,0xd6}, // Power up LDAC/RDAC
    { 0,0x01}, // Select Page 1
    { 9,0x30}, // Power up HPL/HPR
    { 0,0x00}, // Select Page 0
    { 64,0x00}, // Unmute LDAC/RDAC
    };

    Thanks for your help!

  • 0 in reply to Greg Tsai
    TI__Mastermind 46195 points

    Greg,

    Yes. If you would like to have PurePath output this every time, modify the settings in the SystemSettingsCode property of the framework.

    Regards,

    J-