set up TLV320AIC3254-slave with WCLK-output

Hi, Oleg,

I have asked my colleague to look into this for you.

-d2

Thank you very much, Don!

I'll wait for the answer of your colleague.

Thank, J Arbona

I understand, in the case (codec - in slave mode) when BCLK is configured to input and WCLK - to the output, codec receives MCLK from BCLK only. I need a different, because I have no time to clock codec from BCLK (I need some time so that to save data to SD card). So I'm going to use the simple slave mode, when BCLK and WCLK are the inputs. I use 10 MHz MCLK, so I try to apply the formula for the timer interrupt - (10 000 000 / 16 000) / 2 (16 000 - sample rate, 2 - for left and right channel). In the interrupt I will change WCLK and accept bytes as host-master:

/ / Code

#pragma vector = TIMER0_A0_VECTOR
__interrupt void CCR0_ISR(void)
{

P3OUT ^= BIT2;                              // wclk   (switch channel)

Rxbyte = UCA0RXBUF;                   // reset rx flag
while ((UCA0IFG & UCTXIFG) == 0);
UCA0TXBUF = 0xFF;                      // for clock BCLK
while ((UCA0IFG & UCRXIFG) == 0); 
Rxbyte = UCA0RXBUF;                   // read first byte in channel

WriteByte(Rxbyte);                          // for further processing

Rxbyte = UCA0RXBUF; 
while ((UCA0IFG & UCTXIFG) == 0); 
UCA0TXBUF = 0xFF; 
while ((UCA0IFG & UCRXIFG) == 0); 
Rxbyte = UCA0RXBUF;

WriteByte(Rxbyte);

} // CCR0_ISR

/ / Code

Will it work properly?
And finally - when I start to receive bytes, at first I get 0x00 (about 200 bytes), and after that I get any values (probably, they are normal). How to avoid these zeros at the beginning of the exchange?

I will be grateful for any advice.

In principle, my code would work, but the frequency WCLK in codec does not coincide with the frequency of the MSP430, the skewing. The solution is to use a signal ADC_MOD_CLK, which can be divided and output from the GPIO (MISO, DOUT). If AOSR set to divide by 128, then ADTS_MOD_TSLK can be divided by 128 and it will fit WCLK. With this signal I can synchronize frequencies in my case - when the MSP430 is master and codec - slave.

There was one more question, I'm trying use codec ASI in DSP mode in msp430-master. Get the following picture:

I'm doing one clock - WCLK rises, do a clock - WCLK drops, take 4 bytes (left and right channel), but if I do not make a clock in the second half of the period, the WCLK does not rise at all. Can this be avoided? If not, I'll use the LJF.

Oleg,

That is correct. You would have to keep sending BCLK for WCLK to work properly as you mention.

Regards,

J-