PCM3070 programming

Thanks J!  I appreciate your help.

I built my own tool to generate an .h file from the cfg file.  Did not know PPS would do that for me.

What do you mean by active buffer?

Can you tell me why the .cfg file has writes to registers that don't exist? Is that a special flag to cause a delay?

#            # reg[  0][  4] = 0x03    ; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
w 30 04 03
#            # reg[  0][254] = 0x0a    ; Delay 10ms for PLL to lock
w 30 fe 0a
#            # reg[  0][ 12] = 0x88    ; MDAC = 8, divider powered on

-Raul

Raul,

That line is meant to be a special code so that PPS or the MCU that interprets the code introduces a delay. The AIC register range is from 0x00-0x7F.

The line in the framework SystemSettingsCode:

reg[  0][254] = 0x0a

Is incorrect. It should be:

reg[  254][  0] = 0x0a

When you compile with this change, it will show in the .cfg as:

d 10

...and in the .h file as:

{ 0x7E, 0x0a }

...which the target MCU should interpret 0x7E as a delay.

Similarly, in SystemSettingsCode, you'll find PROGRAM_DAC and PROGRAM_ADC. There will generate the following in the .h file:

{ 0x7F, 0x00 }   // Tells the MCU to dowload miniDSP_A array of reg_value.

and

{ 0x7F, 0x01 }   // Tells the MCU to dowload miniDSP_D array of reg_value.

These two are handled automatically for the .cfg output (i.e. the code is flattened out).

Regards,

J-

J,

Thanks for that clue.  That explains the 0x7E.   I do not see any writes to address 7F  in my .cfg file. So I assume

there is no DSP array to download.  Is there any documentation on this?

What did you mean by "active page" in your original response?  Is this something I need to worry about when I configure the 3070 on our target HW?

-Raul

Raul,

You don't see 0x7F writes in the .cfg file because the miniDSP code is already included in there. If you generate a header file (.h) as described above, you'll see what I mean.

Regards,

J-