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Configuring AIC3204 for 8Khz Mono ADC and also DAC

Other Parts Discussed in Thread: TLV320AIC3110

Hi 
 im using aic3204 on a ezDSP C5515  based design board,in the event of trying to capture audio from the codec and feeding that pcm data to speex open source codec

i doubt the codec configurations done i use a electret (2 wired ) micro phone usually it requires mic bias and im using to LDO for that purpose  my configuration code as follows

/* ------------------------------------------------------------------------ *

* Configure AIC3204 *
* Set of Values: NADC=10;MADC=3;AOSR=128;R=2;P=1;J=1;D=28; *
* PLL_CLKIN =12Mhz *
* CODEC_CLKIN = PLL CLK=30720000 *
* CODEC_CLKIN = NADC * MADC * AOSR * ADCFS =10*3*128*8000 *
* PLL_CLK = PLL_CLKIN * R * J.D / P = 12000000*2*1.28/1=3072000 *
* PLL_CLKIN = MCLK = 12MHz *
* ADCFS = 8KHz *
* ------------------------------------------------------------------------ */

//1.Software Reset
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 1, 1 ); // Reset codec
USBSTK5515_wait_Test( 200 ); // Wait
AIC3204_rset( 0, 1 ); // Point to page 1
AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power

// 2.PLL and Clocks Dividers configuration and Power Up For 8KHz Sampling Rate
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence
AIC3204_rset( 28, 0x00 ); // Data ofset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 1 ); // PLL setting: J = 1
AIC3204_rset( 7, 0x00 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0x1c ); // PLL setting: LO_BYTE(D)
//AIC3204_rset( 30, 0x88 ); // BCLK N Divider ->> DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x12 ); // PLL setting: Power up PLL, P=1 and R=2
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 ->> Use with PRB_R1 to PRB_R6, ADC Filter Type A)
AIC3204_rset( 18, 0x8A ); // Power up NADC and set NADC value to 10
AIC3204_rset( 19, 0x83 ); // Power up MADC and set MADC value to 3

//3.Processing Blocks Configuration
AIC3204_rset( 0, 0 ); // Select page 0
AIC3204_rset(61,5); //Select PRB_R5

//4.ADC ROUTING and Power Up

AIC3204_rset( 0, 1 ); // Select page 1
AIC3204_rset(10,0x43); //common mode control register
AIC3204_rset(51,0x68); //MicBias = LDO_IN
AIC3204_rset( 55, 0xc0 ); // IN2_R to RADC_P through 40 kohmm
AIC3204_rset( 54, 0x03 ); // CM_1 (common mode) to LADC_M through 40 kohm
AIC3204_rset( 57, 0xc0 ); // CM_1 (common mode) to RADC_M through 40 kohm
AIC3204_rset( 59, 0x5f ); // MIC_PGA_L unmute
AIC3204_rset( 60, 0x5f ); // MIC_PGA_R unmute
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 81, 0xc0 ); // Powerup Left and Right ADC
AIC3204_rset( 82, 0x00 ); // Unmute Left and Right ADC

AIC3204_rset( 0, 0x00 );

*/
USBSTK5515_wait_Test( 200 ); // Wait
prints("\rCodec Initialization done \n");
/* I2S settings */
I2S2_SRGR = 0x0015;
I2S2_ICMR = 0x0028; // Enable interrupts
I2S2_CR = 0x8012; // 16-bit word, Master, enable I2C
prints("\rI2S Initialization done\n");

 

Even the Configuration seems OK i am not able to take any valid input data from the codec,if i want to check the loop back how could i do for this configuration, Kindly please resolve my problem.

  • Hi, Shyam,

    I've asked my colleague to look into this for you.

    -d2

  • Hi Shyam:

         There are some problems in your setting:

         1.You don't power on the PLL power. So the PLL will not output anything.

         2.CODEC_CLKIN = PLL CLK=30720000 but your configuration is not that value.

  • Please see the picture below:

  • Thanks for you immediate concern Derek Xie

    yeah i have changed the settings of the code slightly and i have provided the external mic bias resistance and they are below but still its not able to capture valid samples 

    // Configure AIC3204
    AIC3204_rset( 0, 0 ); // Select page 0
    AIC3204_rset( 1, 1 ); // Reset codec
    USBSTK5515_wait_Test( 200 ); // Wait
    AIC3204_rset( 0, 1 ); // Point to page 1
    AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
    AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power
    AIC3204_rset( 0, 0 ); // Select page 0
    // PLL and Clocks config and Power Up
    AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence
    AIC3204_rset( 28, 0x00 ); // Data ofset = 0
    AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
    AIC3204_rset( 6, 4 ); // PLL setting: J = 4
    AIC3204_rset( 7, 0x17 ); // PLL setting: HI_BYTE(D)
    AIC3204_rset( 8, 0xc0 ); // PLL setting: LO_BYTE(D)
    AIC3204_rset( 30, 0x88 ); // BCLK N Divider ->> DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
    AIC3204_rset( 5, 0xA4 ); // PLL setting: Power up PLL, P=2 and R=4
    AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR)
    AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR)
    AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 ->> Use with PRB_R1 to PRB_R6, ADC Filter Type A)
    AIC3204_rset( 11, 0x80+36 ); // Power up NDAC and set NDAC value to 36
    AIC3204_rset( 12, 0x83 ); // Power up MDAC and set MDAC value to 3
    AIC3204_rset( 18, 0x80+36 ); // Power up NADC and set NADC value to 36
    AIC3204_rset( 19, 0x83 ); // Power up MADC and set MADC value to 3

    // DAC ROUTING and Power Up
    AIC3204_rset( 0, 0x01 ); // Select page 1
    AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
    AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
    AIC3204_rset( 0, 0x00 ); // Select page 0
    AIC3204_rset( 64, 0x02 ); // Left vol=right vol
    AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
    AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
    AIC3204_rset( 0, 0x01 ); // Select page 1
    AIC3204_rset( 16, 6 ); // Unmute HPL , 6dB gain
    AIC3204_rset( 17, 6 ); // Unmute HPR , 6dB gain
    AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
    AIC3204_rset( 0, 0x00 ); // Select page 0
    USBSTK5515_wait_Test( 500 ); // Wait
    // ADC ROUTING and Power Up
    AIC3204_rset( 0, 1 ); // Select page 1
    AIC3204_rset(10,0x43); //common mode control register
    AIC3204_rset(51,0x68); //MicBias = LDO_IN

    AIC3204_rset( 52, 0x30 ); // IN1_L Routed to Left PGA - For new AED board (03) Left +
    AIC3204_rset( 54, 0xC0 ); // CM_1 (common mode) to LADC_M through 40 kohm Left -
    AIC3204_rset( 59, 80 ); // MIC_PGA_L unmute Left Mic PGA = 40 dB

    AIC3204_rset( 81, 0x80 ); // Powerup Left
    AIC3204_rset( 82, 0x08 ); // Unmute Left and Mute Right

    please i need your comments by the way i have installed the software AIC3204 CS ,wont i be able to access the software if i dont have the EVM ?

    is there any other way to fastly configure the AIC3204 TI engineers must look at this issue

  • Hi Shaym:

              1. What's your input? Mic or Line in? If it's Mic, how do you connect the MIC and the MIC is the IN2L input?

              2. Check whether the clock is right, including the MCLK, WCLK, BCLK. You can also check whether it has Dout output.

              3. If you want to Analog in and analog output, you should configure the page 0, register 0x1D to 0x10.

              And you mute the ADC.... The MIC or the Line in from the IN2_L?Single ended?

    If you don't have the EVM. You will not get the data from the software..

  • Hi Shaym:

                    If you want to fast setting the AIC3204, you can use the picture below:

              

               You can get the code from the script. And the hardware connection should be like the EVM.

  • Derek Xie said:

    Hi Shaym:

         Q     1. What's your input? Mic or Line in? If it's Mic, how do you connect the MIC and the MIC is the IN2L input?

         A.      my input is through AIC line 2L,so mic in goes to left channel ?   

         Q   2. Check whether the clock is right, including the MCLK, WCLK, BCLK. You can also check whether it has Dout output.

         A. clock is also ok i enable it through software for the codec to function as it will be use ful in powerconsumption 

        Q   3. If you want to Analog in and analog output, you should configure the page 0, register 0x1D to 0x10.

                   And you mute the ADC.... The MIC or the Line in from the IN2_L?Single ended?
           

             A. my configuration is as shown in above figure no change with it 

    If you don't have the EVM. You will not get the data from the software..

      :( this is miserable :)

  • Hi Shyam:

                     1. I suggest you use the PGA, because usually the MIC's input is very small. 

                     2.  If you mute the ADC, you will not hear the voice at the output.

                     Can the codec work normally now?

  • yeah i respect your suggestions 

    i still need more suggestions 

    my programs flow 

    1.Take pcm data from aic3204(what diff it will be if i config as master or slave ?)

    2.read the data through i2s interface as shown in ezDSp c5515

    3.send that 16bit sample to the codec( iam using speex)

    4.get the compressed data and send it through UART

    targets 2,3,4 are any ways coded well and checked

     thing remained is achievement 1 .....now i want to start it very clear the configuration manual clearly says 

    step1:software reset done any ways

    AIC3204_rset( 0, 0 ); // Select page 0
    AIC3204_rset( 1, 1 ); // Reset codec
    USBSTK5515_wait_Test( 200 ); // Wait
    AIC3204_rset( 0, 1 ); // Point to page 1
    AIC3204_rset( 1, 8 ); // Disable crude AVDD generation from DVDD
    AIC3204_rset( 2, 1 ); // Enable Analog Blocks, use LDO power

    step2:clock and pll settings for 8Khz signal

    AIC3204_rset( 0, 0 ); // Select page 0
    AIC3204_rset( 27, 0x0d ); // I2S interface, 16 Bit, BCLK and WCLK is set as o/p ,DOUT High Impedence
    AIC3204_rset( 28, 0x00 ); // Data ofset = 0
    AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
    AIC3204_rset( 6, 4 ); // PLL setting: J = 4
    AIC3204_rset( 7, 0x17 ); // PLL setting: HI_BYTE(D)
    AIC3204_rset( 8, 0xc0 ); // PLL setting: LO_BYTE(D)
    AIC3204_rset( 30, 0x88 ); // BCLK N Divider ->> DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
    AIC3204_rset( 5, 0xA4 ); // PLL setting: Power up PLL, P=2 and R=4
    AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR)
    AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR)
    AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 ->> Use with PRB_R1 to PRB_R6, ADC Filter Type A)
    AIC3204_rset( 11, 0x80+36 ); // Power up NDAC and set NDAC value to 36
    AIC3204_rset( 12, 0x83 ); // Power up MDAC and set MDAC value to 3
    AIC3204_rset( 18, 0x80+36 ); // Power up NADC and set NADC value to 36
    AIC3204_rset( 19, 0x83 ); // Power up MADC and set MADC value to 3

     step3:confiuring processing blocks by default it is A so there is not need for me to set it

    in my case i want to configure for both loop back testing and also capture(it can happen ?)

    step4:ADC routing and power up

    AIC3204_rset( 0, 1 ); // Select page 1
    AIC3204_rset(10,0x43); //common mode control register
    AIC3204_rset(51,0x68); //MicBias = LDO_IN

    AIC3204_rset( 52, 0x30 ); // IN1_L Routed to Left PGA - For new AED board (03) Left +
    AIC3204_rset( 54, 0xC0 ); // CM_1 (common mode) to LADC_M through 40 kohm Left -
    AIC3204_rset( 59, 80 ); // MIC_PGA_L unmute Left Mic PGA = 40 dB
    AIC3204_rset( 81, 0x80 ); // Powerup Left
    AIC3204_rset( 82, 0x08 ); // Unmute Left and Mute Right

    step 5:DAC routing and power up

    AIC3204_rset( 0, 0x01 ); // Select page 1
    AIC3204_rset( 12, 0x08 ); // LDAC AFIR routed to HPL
    AIC3204_rset( 13, 0x08 ); // RDAC AFIR routed to HPR
    AIC3204_rset( 0, 0x00 ); // Select page 0
    AIC3204_rset( 64, 0x02 ); // Left vol=right vol
    AIC3204_rset( 65, 0x00 ); // Left DAC gain to 0dB VOL; Right tracks Left
    AIC3204_rset( 63, 0xd4 ); // Power up left,right data paths and set channel
    AIC3204_rset( 0, 0x01 ); // Select page 1
    AIC3204_rset( 16, 6 ); // Unmute HPL , 6dB gain
    AIC3204_rset( 17, 6 ); // Unmute HPR , 6dB gain
    AIC3204_rset( 9, 0x30 ); // Power up HPL,HPR
    AIC3204_rset( 0, 0x00 ); // Select page 0

    i have choose to listen the audio from right left and my mic in also comes from line 2 left so i have unmuted left and muted right  

    next i have to configure my I2S where c55 must be configured as slave to listen to aic3204 

    Slave settings:

    I2S2_SRGR = 0x0015;
    I2S2_ICMR = 0x0028; // Enable interrupts
    I2S2_CR = 0x8010; // 16-bit word, Slave, enable I2C

    i have explained as much i can ,thing is why am i not able to get valid voice data,your question how did i confirm as i said the data i am sending on to UART is not valid thus i have confirmed that i am not capturing valid voice data something must be done to my aic3204 settings

     

  • Hi Shyam:

             For initialization, You can refer to the attached file. 

    ;-----------------------------------------------------------------------------------
    ; Software Reset
    ;-----------------------------------------------------------------------------------
    	reg[  0][  1] = 0x01	; Initialize the device through software reset
           reg[254][  0] = 0x0a	; Delay 10ms
    
    ;-----------------------------------------------------------------------------------
    ; Configure Power Supplies
    ;-----------------------------------------------------------------------------------
    	%%if (%%prop(TargetBoard) == 2)
    ; AIC3254EVM-U specific configuration
    
    	reg[  1][  2] = 0xa9	; Power up AVDD LDO
    	reg[  1][  1] = 0x08	; Disable weak AVDD to DVDD connection
    	reg[  1][  2] = 0xa1	; Enable Master Analog Power Control, AVDD LDO Powered
            
    	%%else
    ; AIC3254EVM-K specific configuration        
    	reg[  1][  1] = 0x08	; Disable weak AVDD to DVDD connection
    	reg[  1][  2] = 0x00	; Enable Master Analog Power Control
            
    	%%endif
            
    	reg[  1][ 71] = 0x32	; Set the input power-up time to 3.1ms   
    	reg[  1][123] = 0x01	; Set REF charging time to 40ms (automatic)
    ;	reg[254][0] = 0x28	; Delay 40ms for REF to Power Up
    
    ;-----------------------------------------------------------------------------------
    ; Load miniDSP Code
    ;-----------------------------------------------------------------------------------
    	PROGRAM_ADC		; miniDSP_A coefficients and instructions           
    	PROGRAM_DAC		; miniDSP_D coefficients and instructions
    
    ;-----------------------------------------------------------------------------------
    ; Signal Processing Settings
    ;-----------------------------------------------------------------------------------
    %%if (%%prop(SynchMode) == 1)
    	; SynchMode is enabled
    	reg[  0][ 60] = 0x80    ; DAC prog Mode: miniDSP_A and miniDSP_D ARE powered up together, miniDSP_A used for signal processing
    %%else
    	; SynchMode is disabled
    	reg[  0][ 60] = 0x00    ; DAC prog Mode: miniDSP_A and miniDSP_D NOT powered up together, miniDSP_A used for signal processing
    %%endif
    	reg[  0][ 61] = 0x00	; Use miniDSP_A for signal processing
    
    	%%if ("%%prop(FrameworkType)" == "AIC3254App8x4x")    
    	reg[  0][ 17] = 0x08	; 8x Interpolation
    	reg[  0][ 23] = 0x04	; 4x Decimation
    	%%endif
    
    	%%if ("%%prop(FrameworkType)" == "AIC3254App4x2x")    
    	reg[  0][ 17] = 0x04	; 4x Interpolation
    	reg[  0][ 23] = 0x02	; 2x Decimation
    	%%endif
    
    	%%if ("%%prop(FrameworkType)" == "AIC3254App2x1x")    
    	reg[  0][ 17] = 0x02	; 2x Interpolation
    	reg[  0][ 23] = 0x01	; 1x Decimation
    	%%endif
    
    	IDAC  = %%prop(miniDSP_D_Cycles)
    	IADC  = %%prop(miniDSP_A_Cycles)
    
    	%%if (%%prop(miniDSP_A_Adaptive) == 1)
    	reg[  8][  1] = 0x04	; adaptive mode for ADC
    	%%endif
    
    	%%if (%%prop(miniDSP_D_Adaptive) == 1)
    	reg[ 44][  1] = 0x04	; adaptive mode for DAC
    	%%endif
    
    ;-----------------------------------------------------------------------------------
    ; Clock and Interface Configuration
    ;-----------------------------------------------------------------------------------
    ; USB Audio supports 8kHz to 48kHz sample rates
    ; An external audio interface is required for 88.2kHz to 192kHz sample rates
    ;-----------------------------------------------------------------------------------
    	%%if (%%prop(SampleRate) == 176400 || %%prop(SampleRate) == 192000)
    	reg[  0][  5] = 0x91	; P=1, R=1, J=8
    	reg[  0][  6] = 0x08	; P=1, R=1, J=8
    	reg[  0][  7] = 0x00	; D=0000 (MSB)
    	reg[  0][  8] = 0x00	; D=0000 (LSB)
    	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
    	reg[  0][ 13] = 0x00	; DOSR = 32 (MSB)
    	reg[  0][ 14] = 0x20	; DOSR = 32 (LSB)
    	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
    	reg[  0][ 19] = 0x88	; MADC = 8, divider powered on
    	reg[  0][ 20] = 0x20	; AOSR = 32
    	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
    
    	%%endif
    
    	%%if (%%prop(SampleRate) == 88200 || %%prop(SampleRate) == 96000)
    	reg[  0][  5] = 0x91	; P=1, R=1, J=8
    	reg[  0][  6] = 0x08	; P=1, R=1, J=8
    	reg[  0][  7] = 0x00	; D=0000 (MSB)
    	reg[  0][  8] = 0x00	; D=0000 (LSB)
    	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
    	reg[  0][ 13] = 0x00	; DOSR = 64 (MSB)
    	reg[  0][ 14] = 0x40	; DOSR = 64 (LSB)
    	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
    	reg[  0][ 19] = 0x88	; MADC = 8, divider powered on
    	reg[  0][ 20] = 0x40	; AOSR = 64
    	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
    	%%endif
    
    	%%if (%%prop(SampleRate) == 44100 || %%prop(SampleRate) == 48000)
    	reg[  0][  5] = 0x91	; P=1, R=1, J=8
    	reg[  0][  6] = 0x08	; P=1, R=1, J=8
    	reg[  0][  7] = 0x00	; D=0000 (MSB)
    	reg[  0][  8] = 0x00	; D=0000 (LSB)
    	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
    	reg[  0][ 13] = 0x00	; DOSR = 128 (MSB)
    	reg[  0][ 14] = 0x80	; DOSR = 128 (LSB)
    	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
    	reg[  0][ 19] = 0x88	; MADC = 8, divider powered on
    	reg[  0][ 20] = 0x80	; AOSR = 128
    	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
    	%%endif
    
    	%%if (%%prop(SampleRate) == 32000)
    	reg[  0][  5] = 0x91	; P=1, R=1, J=8
    	reg[  0][  6] = 0x08	; P=1, R=1, J=8
    	reg[  0][  7] = 0x00	; D=0000 (MSB)
    	reg[  0][  8] = 0x00	; D=0000 (LSB)
    	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
    	reg[  0][ 13] = 0x00	; DOSR = 192 (MSB)
    	reg[  0][ 14] = 0xc0	; DOSR = 192 (LSB)
    	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
    	reg[  0][ 19] = 0x8c	; MADC = 12, divider powered on
    	reg[  0][ 20] = 0x80	; AOSR = 128
    	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
    	%%endif
    
    	%%if (%%prop(SampleRate) == 22050 || %%prop(SampleRate) == 24000)
    	reg[  0][  5] = 0x91	; P=1, R=1, J=8
    	reg[  0][  6] = 0x08	; P=1, R=1, J=8
    	reg[  0][  7] = 0x00	; D=0000 (MSB)
    	reg[  0][  8] = 0x00	; D=0000 (LSB)
    	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
    	reg[  0][ 13] = 0x01	; DOSR = 256 (MSB)
    	reg[  0][ 14] = 0x00	; DOSR = 256 (LSB)
    	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
    	reg[  0][ 19] = 0x90	; MADC = 16, divider powered on
    	reg[  0][ 20] = 0x80	; AOSR = 128
    	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
    	%%endif
    
    	%%if (%%prop(SampleRate) == 16000)
    	reg[  0][  5] = 0x91	; P=1, R=1, J=24
    	reg[  0][  6] = 0x18	; P=1, R=1, J=24
    	reg[  0][  7] = 0x00	; D=0000 (MSB)
    	reg[  0][  8] = 0x00	; D=0000 (LSB)
    	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
    	reg[  0][ 13] = 0x01	; DOSR = 384 (MSB)
    	reg[  0][ 14] = 0x80	; DOSR = 384 (LSB)
    	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
    	reg[  0][ 19] = 0x98	; MADC = 24, divider powered on
    	reg[  0][ 20] = 0x80	; AOSR = 128
    	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
    	%%endif
    
    	%%if (%%prop(SampleRate) == 11025)
    	reg[  0][  5] = 0x91	; P=1, R=1, J=16
    	reg[  0][  6] = 0x10	; P=1, R=1, J=16
    	reg[  0][  7] = 0x00	; D=0000 (MSB)
    	reg[  0][  8] = 0x00	; D=0000 (LSB)
    	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
    	reg[  0][ 13] = 0x02	; DOSR = 512 (MSB)
    	reg[  0][ 14] = 0x00	; DOSR = 512 (LSB)
    	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
    	reg[  0][ 19] = 0xa0	; MADC = 32, divider powered on
    	reg[  0][ 20] = 0x80	; AOSR = 128
    	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
    	%%endif
    
    	%%if (%%prop(SampleRate) == 8000)
    	reg[  0][  5] = 0x91	; P=1, R=1, J=24
    	reg[  0][  6] = 0x18	; P=1, R=1, J=24
    	reg[  0][  7] = 0x00	; D=0000 (MSB)
    	reg[  0][  8] = 0x00	; D=0000 (LSB)
    	reg[  0][  4] = 0x03	; PLL_clkin = MCLK, codec_clkin = PLL_CLK, PLL on
    	reg[  0][ 12] = 0x88	; MDAC = 8, divider powered on
    	reg[  0][ 13] = 0x03	; DOSR = 768 (MSB)
    	reg[  0][ 14] = 0x00	; DOSR = 768 (LSB)
    	reg[  0][ 18] = 0x02	; NADC = 2, divider powered off
    	reg[  0][ 19] = 0xb0	; MADC = 48, divider powered on
    	reg[  0][ 20] = 0x80	; AOSR = 128
    	reg[  0][ 11] = 0x82	; NDAC = 2, divider powered on
    	%%endif
    
    
    
    ;-----------------------------------------------------------------------------------
    ; ADC Channel Configuration
    ;-----------------------------------------------------------------------------------
    	reg[  1][ 51] = 0x40	; Mic Bias enabled, Source = Avdd, 1.25V
    
    	%%if (%%prop(TargetBoard) == 2)
    ; AIC3254EVM-U specific configuration
    	reg[  1][ 52] = 0x10	; Route IN2L to LEFT_P with 10K input impedance
    	reg[  1][ 54] = 0x40	; Route CM1L to LEFT_M with 10K input impedance
    	reg[  1][ 55] = 0x10	; Route IN2R to RIGHT_P with 10K input impedance
    
    	%%else
    ; AIC3254EVM-K specific configuration
    	reg[  1][ 52] = 0x40	; Route IN1L to LEFT_P with 10K input impedance
    	reg[  1][ 54] = 0x40	; Route CM1L to LEFT_M with 10K input impedance
    	reg[  1][ 55] = 0x40	; Route IN1R to RIGHT_P with 10K input impedance
    
    	%%endif
    	
    	reg[  1][ 57] = 0x40	; Route CM1R to RIGHT_M with 10K input impedance
    	reg[  1][ 59] = 0x00	; Enable MicPGA_L Gain Control, 0dB
    	reg[  1][ 60] = 0x00	; Enable MicPGA_R Gain Control, 0dB
    	reg[  0][ 81] = 0xc0	; Power up LADC/RADC
    	reg[  0][ 82] = 0x00	; Unmute LADC/RADC
    
    ;-----------------------------------------------------------------------------------
    ; DAC Channel Configuration
    ;-----------------------------------------------------------------------------------
    	reg[  1][ 20] = 0x25	; De-pop: 5 time constants, 6k resistance
    	reg[  1][ 12] = 0x08	; Route LDAC to HPL
    	reg[  1][ 13] = 0x08	; Route RDAC to HPR
    	reg[  1][ 14] = 0x08	; Route LDAC to LOL
    	reg[  1][ 15] = 0x08	; Route LDAC to LOR
    	reg[  0][ 63] = 0xd4	; Power up LDAC/RDAC w/ soft stepping
    	reg[  1][ 16] = 0x00	; Unmute HPL driver, 0dB Gain
    	reg[  1][ 17] = 0x00	; Unmute HPR driver, 0dB Gain
    	reg[  1][ 18] = 0x00	; Unmute LOL driver, 0dB Gain
    	reg[  1][ 19] = 0x00	; Unmute LOR driver, 0dB Gain
    	reg[  1][  9] = 0x3c	; Power up HPL/HPR and LOL/LOR drivers
    	reg[  0][ 64] = 0x00	; Unmute LDAC/RDAC

            AIC3204_rset( 81, 0x80 ); // Powerup Left
            AIC3204_rset( 82, 0x08 ); // Unmute Left and Mute Right 

             is at  the page 0, but you configure at the page 1...

             Be careful the page which you configure....

             Check the MIC connection. You can refer to our EVM, because I can't see your MIC connection in your schematic, or you can use the line in instead to check.

    If you want to configure ADC to DAC, you should configure :

    Digital loop, which put the ADC's data to DAC. Or the ADC's data will not send to DAC side.

    w 30 00 00
    w 30 1D 20

    You can test the Dout at the AIC3204 to see whether have data output, to make sure the chip work. 

            

  • Very thanks for your immense help, never thought  that a TI engineer would help this much to a beginner 

     Be careful the page which you configure...

    This is what wasted my 2 days time,but one more problem has arise the data which is coming from left channel should go in to LSW or MSW ? in my case i am seeing it in MSW is that right?

           more over my speech codec engine speex expects a signed value of PCM but AIC gives us 2s complement value how to manage with it,as now speex has become absolute there is no one to comment on it any TI engineer has worked with speex could help me ? how could i approach ?

  • Hi 

          What do you mean about the LSW and MSW? Is the MSB and LSB?

          Because the audio interface is I2S format, actually the I2S is also PCM signal which has some offset in some mode. I think you can try to use DSP mode.

          Receive the data and do some shifting at the data, you will get the data you want.

          

  • yeah i am seeing the data in MSB is that desired ? 

    and DSP format and i2s doesnt make any difference can you please refer any TI engineer who worked on speech codecs if possible at least on any codec

  • Hi 

           Right,  MSB is first.

    In fact, I2S data and PCM data are similar. If you can set a counter to get the data which you want.

    BCLK like the PCM clock, the WCLK like the syc clock.

    And TI also has PCM Codec. Like TLV320AIC3110.

            

  • A "signed value" typically means twos complement and that is what the AIC3204 will provide. i.e. the AIC3204 will provide you with an Int16, most significant bit first, across I2S.