PCM3070 - Audio Mixing configuration

Winnefred,

There are example configuration settings in this app note: http://www.ti.com/litv/pdf/slaa404c.

Things to keep an eye for:

1) An external MCLK is required if using the ADC and DAC converters. I see pin 1 disconnected in the schematic.

2) Your setup does not use I2S to communicate to other chips. In such case, the BCLK and WCLK must be set as outputs (master mode) if using ADCs and DACs. See app note for an example script.

3) You setup assumes use of internal ALDO and DLDO. See app note for an example script.

Regards,

J-

Winnefred,

Here is an example script for analog stereo PGA bypass. You'd need to modify it for ALDO use and for your specific routings.

For SPI, ignore the '30'. The second byte is the register value in hex and subsequent bytes are data.

Regards,

J-

###############################################
# PGA Analog Bypass
# ---------------------------------------------
# This script routes IN1_L/R inputs to HPL/R
# outputs through MicPGA. Connect a portable
# media player to J1 (IN1_L/R) and headphones
# to J9.
#
# Ensure the input signal does not exceed the
# maximum rated input voltage.
###############################################

###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################

###############################################
# Initialize Codec
###############################################
#
# Select Page 1
w 30 00 01
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
w 30 02 00
#
# Set the input powerup time to 3.1ms (for ADC)
# w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################

###############################################
# Playback Setup
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop
w 30 14 25
#
# Route IN_1L to Left MicPGA P
w 30 34 40
w 30 36 40
#
# Route IN_1R to Right MicPGA P
w 30 37 40
w 30 39 40
#
# Mixer Amp -> HP outs
w 30 0C 02 02
#
# Mixer Amp -> Lineouts
w 30 0E 02 02
#
# PGA Bypass Gain = 0dB
w 30 18 00 00
#
# Power up HPL/HPR, LOL/LOR and MAL/MAR drivers
w 30 09 3F
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
#
# Unmute LOL/LOR driver, 0dB Gain
w 30 12 00 00
#
###############################################

Hi,

First, I notice that pin 18 (REF) connection is incorrect. It should only be connected to a cap and not to VDD.

From power supply perspective, worst case assume 50mA for DVDD LDO + 50mA for AVDD LDO running out of LDOIN supply. On top of that, if you plan to power HP amplifiers out of LDOIN pin directly, then worst case for this is ~250mA assuming 64mW per channel into 16-ohm loads and 50% efficiency of class-AB amps (conservative). So 250+100 = 350mA worst case off 3.3V. In reality, 250mA is typically ok.

For typical usage without complex miniDSP algorithms, expect ~10mA quiescent when having both ADCs/DACs running.

Regards,

J-

Daniel,

For the processing engine to work, BCLK and WCLK must be present either externally or internally. For this case, you would then need to set BCLK and WCLK as outputs. This document describes how to accomplish this in the Appendix section (as sample scripts): http://www.ti.com/lit/pdf/slaa404.

Regards,

J-