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TLV320AIC3204: Help needed configuring secondary audio bitclk

RobK
Prodigy 230 points
Other Parts Discussed in Thread: TLV320AIC3204

Hello,

I have a custom PCB with a TLV320AIC3204 audio codec. I have the primary audio bus set as I2S master and connected to my microcontroller. The codec is configured through the I2C data bus. This part works fine.

Here's the part that doesn’t work: I also have some of the CODECs MFP pins connected to a header which then goes to a piece of audio test equipment. I'm hoping to get these pins working as the secondary audio bus (also I2S) so I can switch to this secondary bus and output digital audio to my test equipment. I'd like to configure the MFP pins as follows:

DIN/MFP1 -> Secondary audio bit clock input

SCLK/MFP3 -> Secondary audio word clock input

MISO/MFP4 -> Secondary audio data output

I understand how to configure the MFP3 and MFP4 pins appropriately, but for the life of me I cannot determine how you're supposed to configure MFP1 as the secondary audio bit clock input. I've been staring at the "Application Reference Guide" (SLAA557) for hours. The best I can figure is to set MFP1 as the PLL Clock input, and then set the PLL Clock as the secondary audio BCLK. But I can't find the proper register combinations to do this.

The datasheet clearly states that MFP1 can be used as a secondary audio serial data bus bit clock input.

Can someone please help me with this?

  • 0
    Prodigy 230 points

    Hello? Can anyone out there help me with this?

  • 0 in reply to RobK
    Prodigy 230 points

    Bump.

  • 0 in reply to RobK
    Prodigy 230 points

    Bumpity bump... bump... bump...

  • 0 in reply to RobK
    TI__Guru**** 189401 points

    Hi, Rob,

    Sorry for the delay...

    Did you get this sorted out, or give up? :)

    -d2

  • 0 in reply to Don Dapkus
    Prodigy 230 points

    Hi Don,

    No, I  haven't gotten it sorted out or given up. Would you be able to help me?

  • 0 in reply to RobK
    TI__Guru**** 189401 points

    Hi, Rob,

    Let me ask my colleagues to chime in.

    -d2

  • 0 in reply to Don Dapkus
    Prodigy 230 points

    I'm waiting with anticipation :)

  • 0 in reply to Don Dapkus
    Prodigy 230 points

    Why is this taking so long? Have I stumped everyone with this question? Or can no one be bothered to answer it?

  • 0
    TI__Mastermind 46195 points

    Rob,

    I see the MFP1 description you mention and it is incorrect. Refer to Table 8 of the d/s for actual options for that pin.

    The best way to visualize the available options is Figure 2-50 of http://www.ti.com/lit/ml/slaa557/slaa557.pdf. Each pin has a register associated with it and each mux as well. One easy way to know which register corresponds to each is by using the control software available in the EVM product folder. Hover on top of the control and it will show a tip strip with the associated register. It is under Digital Settings > Clocks / Interface > Audio Interface. You also need to configure the pins themselves.

    *correction in red below*

    The problem with using MFP1 as PLL Input for S_BCLK input is that timing will not match correctly wrt S_WCLK and S_DOUT.

    The ideal way of doing your configration is using GPIO = BCLK2, SCLK = WCLK2, MISO = DOUT2. Note that there are also implications on using I2S as input since the converters' master clock need to be sync'd with I2S. To achieve proper sync, you can use BCLK2 (GPIO mentioned here) as PLL input. See http://www.ti.com/litv/pdf/slaa469.

    Regards,

    J-

  • 0 in reply to J-
    Prodigy 230 points

    Hi J,

    Thanks for your help. It's unfortunate that the DIN/MFP1 pin is misrepresented in the datasheet, and I hope this will be corrected so no one else makes the same mistake. I've already looked into cutting some traces on my REVA board and re-wiring to implement the setup you suggest. I'll report back with the results.

    I see what you mean about having the secondary I2S bus BCLK and WCLK as inputs, and them not being synchronous with MCLK. Ideally BCLK2 and WCLK2 would both be outputs, and both generated from MCLK so everything would be synced up. But frustratingly enough there seems to be no way to do this. The only option would be to use DOUT/MFP2, but MFP2 is useless since it's on the same pin as the primary data output. Why? This seems like a major oversight. Of course I didn’t design the chip so I won’t pretend to know better, but it certainly would have made my application easier.

  • 0 in reply to RobK
    TI__Mastermind 46195 points

    Hi Rob,

    First, see correction to my previous post.

    I cannot tell you what the designers had in mind at that moment, but keep in mind the amount of pins available for multi-function purposes. There are trade-offs in design...for example, you could not use the secondary I2S if you're using SPI. Another one is that SCLK is only an input so it cannot be used as output. If you think about it, you could also have your setup working as master mode using DOUT as S_WCLK. But this requires to have the first I2S chip ignore the S_WCLK switching activity in its RX pin connected to DOUT of AIC device.

    Again, Figure 2-50 of the reference guide will provide all the available configuration possible.

    Feel free to ask us questions. We'll try to answer them as soon as possible.

    Regards,

    J-