Issue with TLV320AIC3106 Codec DOUT pin - No data

Hi,

It is not clear from this what inputs are connected in hardware, however, there are a couple of other problems. Neither ADC is turned on in Registers 19, and 22. Also the Right PGA is not unmuted in Register 16. 

HI experts,

             Thanks for the reply. Sorry for pasting the playback register configuration dump in the previous post, here are the TLV320AIC3106 register configuration for capturing on using "arecord" :

tlv320aic3x register values:                                              
1-AIC3X_RESET 80                                                          
2-AIC3X_SAMPLE_RATE_SEL_REG 0                                             
3-AIC3X_PLL_PROGA_REG 1                                                   
4-AIC3X_PLL_PROGB_REG 1c                                                  
5-AIC3X_PLL_PROGC_REG 52                                                  
6-AIC3X_PLL_PROGD_REG 40                                                  
7-AIC3X_CODEC_DATAPATH_REG 8a                                             
8-AIC3X_ASD_INTF_CTRLA 0                                                  
9-AIC3X_ASD_INTF_CTRLB 0                                                  
10-AIC3X_ASD_INTF_CTRLC 0                                                 
11-AIC3X_OVRF_STATUS_AND_PLLR_REG 1                                       
12-AIC3X_CODEC_DFILT_CTRL 0                                               
13-AIC3X_HEADSET_DETECT_CTRL_A 0                                          
14-AIC3X_HEADSET_DETECT_CTRL_B 0                                          
ADC PGA control registers ->                                              
15-LADC_VOL 0                                                             
16-RADC_VOL 0                                                             
MIC Control registers                                                     
17-MIC3LR_2_LADC_CTRL ff                                                  
18-MIC3LR_2_RADC_CTRL ff                                                  
Line1L Input Control Registers->                                          
19-LINE1L_2_LADC_CTRL 4                                                   
20-LINE2L_2_LADC_CTRL 78                                                  
21-LINE1R_2_LADC_CTRL 0                                                   
22-LINE1R_2_RADC_CTRL 4                                                   
23-LINE2R_2_RADC_CTRL 78                                                  
24-LINE1L_2_RADC_CTRL 0                                                   
25-Mic Bias control MICBIAS_CTRL 0                                        
26-LAGC_CTRL_A 0                                                          
27-LAGC_CTRL_B fe                                                         
28-LAGC_CTRL_C 0                                                          
29-RAGC_CTRL_A 0                                                          
30-RAGC_CTRL_B fe                                                         
31-RAGC_CTRL_C 0                                                          
34-ADC_FLAGS 0                                                            
35-LINE2L_2_LADC_CTRL 78                                                  
36-ADC Flag register 0                                                    
37-DAC_PWR 0                                                              
38-HPRCOM_CFG 0                                                           
43-LDAC_VOL 80                                                            
44-RDAC_VOL 80                                                            
47-DACL1_2_HPLOUT_VOL af                                                  
51-HPLOUT_CTRL c                                                          
58-HPLCOM_CTRL c                                                          
64-DACR1_2_HPROUT_VOL af                                                  
65-HPROUT_CTRL c                                                          
72-HPRCOM_CTRL c                                                          
82-DACL1_2_LLOPM_VOL af                                                   
86-LLOPM_CTRL 8                                                           
92-DACR1_2_RLOPM_VOL af                                                   
93-RLOPM_CTRL 8                                                           
94-MODULE_PWR_STATUS 0                                                    
95-Output Driver Short Circuit Detection Status Reg 0                     
96-AIC3X_STICKY_IRQ_FLAGS_REG 0                                           
97-AIC3X_RT_IRQ_FLAGS_REG 0                                               
98-AIC3X_GPIO1_REG0                                                       
102-AIC3X_CLKGEN_CTRL_REG 2                                               
108-PASSIVE_BYPASS 11                                                     
108-PASSIVE_BYPASS 11 

             We would also like to give the following information , which will help you to debug the issue for us,

             1. Line1LP and LIne1RP are alone available as inputs ( Hence, Line1RM, Line1LM, Line2LP, Line2RP, LIne2LM, Line2RM, MIc3R, Mic3L are all connected to GND).

             2. MicBIAS is not connected

             3. DVDD = 1.8V, AVDD_DAC = 3V, AVSS_ADC = GND, AVSS_DAC= GND,

             4. MCLK = 12MHz, WCLK and BCLK are configured as inputs.

             Also refer to the schematic for more information on the connected pins.

            From the above register dump, Left and Right ADC are powered on and unmuted.

            Please tell us the required TLV320AIC3106 register configurations that need to be done or any other changes required at the hardware level.

Thanks,

Dhiv.

Hi,

      Thanks for the input. We also tried enabling PLL. Still we dont see any signal on DOUT pin on recording. It will be of great help if you tell us how to debug further.

Thanks,

Dhiv

I would typically start by checking all of the clocks (MCLK, WCLK, BCLK), If those look ok, I would try an I2C sniffer to see what is actually being written to the registers and also the sequence that they are being written in (this insures that there isn't something wrong in the C code). If you can send the I2C log, we can have a look.

Hi,

    On checking the signals by probing, we see the BCLK signal , but no WCLK  and DOUT signal on recording. Can the codec be configured to send the data based on the bit clock and data len per frame, since WCLK is not sent by the master for data transmission ? On playback which already works fine, we see WCLK, BCL and DIN signals. We will try to debug on this further and thank you so much for all time and effort you have taken in helping us so far.

Thanks,

Dhiv.

WCLK is required.

Hi expert,

Many thanks for guiding us in debugging the issue. After making hardware changes, we are able to get the WCLK signal generated. On recording, now the codec is sending the data and we are seeing the signal on DOUT pin. But the issue is that the quality of sound is not good on recording with sampling rate 44100, 16Bit Little endian format in channel 1, even on trying with different PGA capture volume, we get more noise and very feeble voice of source being recorded.

Thanks & appreciation,

Dhiv.

How do you verify that the WCLK is sync'd to the CODEC? When the PLL is used to generate the clocking, it is best to have the CODEC as the master for WCLK since otherwise there is no easy way to insure that the sample rate determined by the PLL will EXACTLY match the external WCLK. This can lead to noise. there is an app note on the subject here:

http://www.ti.com/lit/an/slaa469/slaa469.pdf

Hi,

    Thanks for the insight. In our case, the Codec is receiving the BCLK and WCLK from the serial interface ( Synchronous Serial Controller), hence PLL is not generating the clock for us. Still we get the volume of the recorded voice very low and with noise. This is not the scenario with playback.

Thanks,

Dhiv.

It looks like you are using the PLL? You are sending values to the PLL registers.

Hi,

    Im sending values to the PLL registers. But the PLL is disabled, hence it is not generating the clocks. In our case, Synchronous Serial Controller (SSC) is the master and generates WCLK and BCLK for the codec.

    Any help to get the noise faded and better voice quality would be great.

Waiting for your reply,

Dhiv.

What is the MCLK frequency?

Hi,

    MCLK frequency is 12Mhz. For any other information on Schematics please refer to the previous post in this discussion.

Thanks in advance,

Dhiv.

Hi,

I saw that your MCLK was 12 MHz in the previous post however, I was hopping you had changed it since you were not using the PLL. If you are using the script above, then your sample rate is 12 MHz / 256 = 46.875 kHz. Your WCLK will have to be at exactly 46.875 kHz or you will have data errors. The sample rate is set by MCLK and the divider ratios (or PLL). The digital audio interface must exactly match this rate. This is detailed in the app note that I sent in a previous post.

Hi experts,

Thanks for all your inputs. It was a timely help for us. Now we have enabled PLL and using it for clock generation, and set Codec in master mode for BCLK and WCLK. Now the playback works with improved quality and plays exactly the same way it has to be played. We are trying on to reduce the noise on recording.

Many more thanks & appreciation,

Dhiv.

Hi experts,

Can you please tell us the way for better recording, with increased signal quality and reduced noise. I have observed that setting lower sample rates reduces the noise considerably. Hence we have tested with 8000Hz sample rate. Also reducing the ADC volume reduces the noise, along with reducing the voice signal volume. We have tried enabling ADC high pass filter with fc = 0.025 * fs. But we are not completely successful on trying all this. Please help us on this. 

Lot of thanks,

Dhiv.