Question about TLV320DAC3100

Please attach the complete register settings showing how you configured all clocks. What's your filter configuration and please attach a plot of the spectrum.

Our register settings are shown in the following:

//Step1. define starting point
 //set page 0
 codec_register[0] = 0;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x00, codec_register, 1);
 //SW reset
 codec_register[0] = 0x01;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x01, codec_register, 1);

//Step2. program clock settings

 codec_register[0] = 0x03;//PLLin = 0 = MCLK, Codec_Clk_in = 0x03 = PLL_CLK as Output
 codec_register[1] = 0xd1;//PLL is On, P = 5, R = 1
 codec_register[2] = 0x0C;//J = 12
 //D is in reg 7 and reg 8, which is default is 0, so dont configure it
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x04, codec_register, 3 );

 //NDAC,MDAC, DOSR setup
 codec_register[0] = 0x83;//NDAC is on, NDAC = 3
 codec_register[1] = 0x85;//MDAC is on, MDAC = 5
 codec_register[2] = 0x00;//DOSR  MSB
 codec_register[3] = 0x7D;//DOSR = 125
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x0b, codec_register, 4);

 codec_register[0]  = 0x40;//DSP, word length 16 bit
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x1B, codec_register, 1);

 //using dac processing block selection PRB_P11
 codec_register[0]  = 0x18;// PRB_P24, PRB_P25 -> 0x19;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x3C, codec_register, 1);
 codec_register[0]  = 0x08;// page 8
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x00, codec_register, 1);
 codec_register[0]  = 0x04;// adaptive filtering enabled in DAC processing block
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x01, codec_register, 1);
 codec_register[0]  = 0x0;// page 0
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x00, codec_register, 1);

//Step3. program analog blocks
 //configure page 1 registers
 codec_register[0]  = 0x01;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x00, codec_register, 1);
 //class D output driver is enabled
 codec_register[0]  = 0x86;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x20, codec_register, 1);
 //DAC L and R to output corresponding mixer
 codec_register[0]  = 0x44;
 codec_register[1] = (1<<7); // left channel analog volume control routed to HPL, 0dB
 codec_register[2] = (1<<7); // Right channel analog volume control routed to HPR, 0dB
 codec_register[3]  = (1<<7) | 0x12;// enable HPL out analog volume, -9dB
 codec_register[4]  = (1<<7) | 0x12;// enable HPR out analog volume, -9dB
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x23, codec_register, 5);
 //left channel analog volume control output is routed to Class-D output driver, analog gain is -9dB
 codec_register[0]  = (1<<7) | 0x34;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x26, codec_register, 1);
 //Umute HPL, HPR, set gain = 0 dB
 codec_register[0] = 0x06;
 codec_register[1] = 0x06;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x28, codec_register, 2);
 //class D, speaker driver gain, 24 db, not muted, not gain applied
 codec_register[0]  = 0x1C;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x2a, codec_register, 1);

//Step4. poll register
 //wait until programed gains to class-D have been applied
 char ClassD_RDY = 0;
 do{
  I2C_1_ReadData(AUDIO_CODEC_ADDRESS, 0x2a, &ClassD_RDY, 1);
  ClassD_RDY &= 0x01;
 }while(!ClassD_RDY);

//Step5. Power up DAC
 //after initialization, set the page to default page(0)
 codec_register[0]  = 0x00;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x00, codec_register, 1);

 //power left and right dac channel
 codec_register[0]  = 0xD6; // 0xDB
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x3F, codec_register, 1);

 unsigned char volume = 0x00;
 codec_register[0] = volume;
 codec_register[1] = volume;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x41, codec_register, 2);

 // unmute DAC left and right channels
 codec_register[0] = 0x00;
 I2C_1_WriteDataOut(AUDIO_CODEC_ADDRESS, 0x40, codec_register, 1);

What's your MCLK frequency and the desired sampling rate?

If you use the processing blocks, you can't set DOSR to 125. DOSR must be an integer multiple of 64 otherwise samples get dropped which may explain your screen shot.

Hi, the MCLK=37.5M, the audio raw data frequency is 20k, so I think the desired sampling rate should lager than 20k, for example 48K.

At this moment, I have changed the DOSR to 128, N = 3, M = 5, P = 3, R = 1, J.D = 7.3287, so that the DAC_fs = 48k, but it still work hard. what can i do now? thanks.

J.D should be 7.3728, not 7.3287 for a 48kSPS rate (with the other parameters the same as from your last reply).

Are you 100% sure that the source data is correct? The jagged lines look like there may be a problem with your digital audio data. The "fuzzy" noise around the main signal in the time domain may be the out of band noise, which is inherent to the architecture and must be filtered with a simple first order RC low-pass with a -3dB cut-off at a few kHz above the band of interest (e.g. at 30kHz). If possible, attach a spectrum, not the time domain scope shot.

Thanks very much for your kind reply.

1. the J.D has already been configured with 7.3728 for 48KHZ

2. I'm not sure that my source data is correct. do you have any correct source data for us to debug ? If you have, can you send them to my email (wzhiwei7@163.com) ? thanks very much

3. I'm trying to obtain the spectrum, i'll attach it latter. 

Hi, the gray lines are the spectrum of single showed in the yellow lines. we used the scope to obtain it, and the Center frequency of the window is 1KHz, the Span is also 1KHz. 

 can you tell me what the spectrum shows? thank you.