Receiver randomly resets

Hi Jim,

I suppose someone has written an audio device definition file (.ppwadd) for the TAS5717 for this project. Can you please post it here? Thank you.

Best regards

Kristoffer

Hello Kristoffer,

Yes, I believe the previous engineer who we inherited this from wrote it, it's dated more recently than the other .ppwadd files. I'll admit I really don't know anything about it, we've just been dealing with stuff as it comes up. Thanks, Jim

<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE audio_device SYSTEM "audio_device_definition.dtd"[]>
<audio_device>
    <name>TAS5717</name>
    <type>Digital amplifier</type>
    <desc>
        TEXAS INSTRUMENTS TAS5717 - 10 W Digital Audio Power Amp With HP EQ and DRC

        IMPORTANT:
        PVDD ramping can be handled externally or by the "Power" control signal.
        Time delays must be adjusted to match the PVDD raming time.
        Strong external pull-down is required for the "Reset" and "Power" control signals.

        DEFAULT SETUP (I2C):
        Serial format: I2S, 16/24-bit, continuous clock, auto sample rate with internal oscillator.
        Outputs: 2x10 W differential outputs (left=A+/B- and right=C+/D-).

        VOLUME CONTROL:
        Output volume: Controls channel 1 and 2 volume, with muting (registers 0x08 and 0x09).
    </desc>
    <datasheet>
        <path>Digital amplifier//TAS5717</path>
        <link>http://www.ti.com/lit/gpn/tas5717</link>
    </datasheet>
    <input_count>0</input_count>
    <output_count>2</output_count>
    <attr_spec name="Hardware platform">PurePath Wireless EB,Custom design</attr_spec>
    <attr_spec name="Interface format" custom_setup="0">I2S</attr_spec>
    <attr_spec name="Interface format" custom_setup="1">I2S,LJF,RJF</attr_spec>
    <attr_spec name="Resolution" custom_setup="0">16,24</attr_spec>
    <attr_spec name="Resolution" custom_setup="1">16,24</attr_spec>
    <attr_spec name="Clock source" custom_setup="0">Internal with MCLK</attr_spec>
    <attr_spec name="Clock source" custom_setup="1">External,Internal with MCLK,Internal without MCLK</attr_spec>
    <attr_spec name="BCLK multiplier" custom_setup="0">32,64</attr_spec>
    <attr_spec name="BCLK multiplier" custom_setup="1">32,64</attr_spec>
    <attr_spec name="MCLK multiplier" custom_setup="0">128,256,384,512</attr_spec>
    <attr_spec name="MCLK multiplier" custom_setup="1">128,256,384,512</attr_spec>
    <attr_spec name="Sample rate">32000,44100,48000</attr_spec>
    <adx_pin_spec dir="Output">
        <io_mapping hardware_platform="PurePath Wireless EB">0100</io_mapping>
        <io_mapping hardware_platform="Custom design">0380</io_mapping>
    </adx_pin_spec>
    <i2c_interface>
        <clock_rate>400</clock_rate>
    </i2c_interface>
    <ctrl_pin_spec name="Reset">
        <io_mapping_name>Audio device reset control</io_mapping_name>
        <io_mapping hardware_platform="PurePath Wireless EB">0004</io_mapping>
        <io_mapping hardware_platform="Custom design">FFFE</io_mapping>
        <initial_setting>0</initial_setting>
        <active_level>0</active_level>
    </ctrl_pin_spec>
    <ctrl_pin_spec name="Power">
        <io_mapping_name>Audio device PVDD control</io_mapping_name>
        <io_mapping hardware_platform="PurePath Wireless EB">FFFA</io_mapping>
        <io_mapping hardware_platform="Custom design">FFFE</io_mapping>
        <initial_setting>0</initial_setting>
        <active_level>1</active_level>
    </ctrl_pin_spec>
    <cfg_sequence_filter_spec name="adx_res_24b">
        <adx_resolution>24</adx_resolution>
    </cfg_sequence_filter_spec>
    <state_cfg_sequence transition="OFF to SR-SWITCH">
        # POWER-UP AND RESET
        d 4              # Wait for 100 us
        p Reset 1        # Release the reset pin
        p Power 1        # Enable PVDD
        d 422            # Wait for 13.5 ms
        # TRIM OSCILLATOR
        w 54 1B 00       # Set factory trim
        d 7500           # Wait for 190 ms (tPLL extra delay after first trim, 50 ms more later on)
        # CONFIGURATION
        -adx_res_24b w 54 04 03       # Interface is 16-bit I2S
        +adx_res_24b w 54 04 05       # Interface is 24-bit I2S
        w 54 1A 13       # Set soft-start and soft-stop period = 403.9 ms
        w 54 08 03 FF    # Channel 1 volume = MUTED
        w 54 09 03 FF    # Channel 2 volume = MUTED
    </state_cfg_sequence>
    <state_cfg_sequence transition="SR-SWITCH 32000 to INACTIVE">
    </state_cfg_sequence>
    <state_cfg_sequence transition="SR-SWITCH 40275 to INACTIVE">
    </state_cfg_sequence>
    <state_cfg_sequence transition="SR-SWITCH 44100 to INACTIVE">
    </state_cfg_sequence>
    <state_cfg_sequence transition="SR-SWITCH 48000 to INACTIVE">
    </state_cfg_sequence>
    <state_cfg_sequence transition="INACTIVE to LOW-POWER">
    </state_cfg_sequence>
    <state_cfg_sequence transition="LOW-POWER to ACTIVE">
        d 1563           # Wait for 50 ms
        w 54 05 00       # Exit shutdown
        d 16440          # Wait for 1 ms + 1.3 * 403.9 ms = 526.1 ms
        w 54 07 00 C0    # Master volume = UNMUTED (0 dB)
    </state_cfg_sequence>
    <state_cfg_sequence transition="ACTIVE to LOW-POWER">
        w 54 08 03 FF    # Channel 1 volume = MUTED
        w 54 09 03 FF    # Channel 2 volume = MUTED
        w 54 05 40       # Enter shutdown
        d 16440          # Wait for 1 ms + 1.3 * 403.9 ms = 526.1 ms
    </state_cfg_sequence>
    <state_cfg_sequence transition="LOW-POWER to INACTIVE">
    </state_cfg_sequence>
    <state_cfg_sequence transition="INACTIVE to SR-SWITCH">
    </state_cfg_sequence>
    <state_cfg_sequence transition="SR-SWITCH to OFF">
        # POWER-DOWN
        p Reset 0        # Assert reset pin
        d 1              # Wait for 2 us
        p Power 0        # Disable PVDD
    </state_cfg_sequence>
    <vol_gain_range_spec dir="Output">-79.0,24.0</vol_gain_range_spec>
    <vol_ctrl_spec dir="Output" type="Mute" io_channel_mask="01">
        <patch_i2c_addr>54</patch_i2c_addr>
        <patch_reg_addr_size>1</patch_reg_addr_size>
        <patch_reg_addr>08</patch_reg_addr>
        <patch_reg_data_size>2</patch_reg_data_size>
        <patch_reg_data>03FF</patch_reg_data>
        <patch_read_mask>0000</patch_read_mask>
    </vol_ctrl_spec>
    <vol_ctrl_spec dir="Output" type="Volume,Unmute" io_channel_mask="01">
        <vol_precision>3</vol_precision>
        <vol_negate>1</vol_negate>
        <vol_add_value>192</vol_add_value>
        <vol_left_shift>16</vol_left_shift>
        <vol_field_size>10</vol_field_size>
        <patch_i2c_addr>54</patch_i2c_addr>
        <patch_reg_addr_size>1</patch_reg_addr_size>
        <patch_reg_addr>08</patch_reg_addr>
        <patch_reg_data_size>2</patch_reg_data_size>
        <patch_reg_data>0000</patch_reg_data>
        <patch_read_mask>0000</patch_read_mask>
    </vol_ctrl_spec>
    <vol_ctrl_spec dir="Output" type="Mute" io_channel_mask="02">
        <patch_i2c_addr>54</patch_i2c_addr>
        <patch_reg_addr_size>1</patch_reg_addr_size>
        <patch_reg_addr>09</patch_reg_addr>
        <patch_reg_data_size>2</patch_reg_data_size>
        <patch_reg_data>03FF</patch_reg_data>
        <patch_read_mask>00</patch_read_mask>
    </vol_ctrl_spec>
    <vol_ctrl_spec dir="Output" type="Volume,Unmute" io_channel_mask="02">
        <vol_precision>3</vol_precision>
        <vol_negate>1</vol_negate>
        <vol_add_value>192</vol_add_value>
        <vol_left_shift>16</vol_left_shift>
        <vol_field_size>10</vol_field_size>
        <patch_i2c_addr>54</patch_i2c_addr>
        <patch_reg_addr_size>1</patch_reg_addr_size>
        <patch_reg_addr>09</patch_reg_addr>
        <patch_reg_data_size>2</patch_reg_data_size>
        <patch_reg_data>0000</patch_reg_data>
        <patch_read_mask>0000</patch_read_mask>
    </vol_ctrl_spec>
</audio_device>

Hi Jim,

Sorry for the delay here, but I think I stumbled onto something. I compared the tas5717.ppwadd you uploaded with the existing tas5727.ppwadd, and I saw that they were identical (except for some naming and description stuff etc.). Then I compared the data sheets of these two devices, and they turned out to be extremely similar (no surprises yet..). Then I read the following in the I2C SERIAL CONTROL INTERFACE chapter:

"The 7-bit address for TAS5717/9 is 0101 010 (0x54) or 0101 011 (0x56) defined by A_SEL (external pulldown for
0x54 and pullup for 0x56). Stero device with Headphone should use 0x54 as its device address."

I suggest you try using the 0x56 address instead since your application is a speaker. I think this can explain the strange things you see..

So every where in your tas5717.ppwadd, replace 54 with 56, for example in this line

 w 54 08 03 FF    # Channel 1 volume = MUTED

change it to 

 w 56 08 03 FF    # Channel 1 volume = MUTED

You also need to pull A_SEL high in order for the address to really be 0x56...

-Kristoffer

Hello Kristoffer,

Sorry for my delay, been tied up. The minute I change the A_SEL on the tas5717 from a 10k pulldown to a pullup, the status led on the cc8520 changes from 20ms on/980ms off to 4ms on/16ms off. This is before any reprogramming. After doing what you suggested, changing the 54s to 56s in the .ppwadd file, and reprogramming, the incorrect led cadence remains.

Also, I have address 54 instructions on the Audio Device Customization page in the Purepath Configurator, and changing the .ppwadd file didn't seem to change them. Should they be changed also? But first I need to find out what the 4ms on/16ms off cadence means.

Thanks, Jim

Hi Jim,

If you click the "Set all sequences to default" button in the Audio device Customization panel the sequences should change to the same as you have in the ppwadd file. Do this and verify that the 54s change to 56. Then try reprogramming and see if the problem is still present.

I guess the LED pattern 20/980 comes from the default ALONE LED pattern defined in the Status Indication panel. If you see anything else than this it probably means that the device is being constantly reset causing "strange" LED behaviour.

Best regards

Kristoffer

Hello Kristoffer,

Well, the 'Set all sequences to default' worked fine after saving and restarting the program, and after reprogramming the receiver the led cadence get back to what it's supposed to be, and the receiver had no problem getting in set with the transmitter, and the audio is fine. So now I need to let it run and see if the random reset problem still exists. I'll let you know, and Thanks Very Much for the help so far.

Thanks, Jim

Hello Kristoffer,

One of the several units our client is testing the pullup/sw changes on just did the random reset, he didn't have an aardvark on that receiver, so I don't have specifics about the I2C transactions. I did notice that the I2C traffic is quite different, longer, now that I'm using the modified .ppwadd for the tas5717, with the 'sequences to default' pressed on the Audio Device Customization screen in the configurator.

There is no power supply noise, no glitches on reset, I've said how we've tried taking the transmitter off frequency, we have also tried sweeping the RF with a Vaunix Lab Brick for interference, to no affect. Any ideas?

Thanks, Jim

Well, a week has gone by, our client is not shipping product, and this is really a proprietary software black box that we have no clue how to fix. Does anyone have any idea how to address this resetting problem? Thanks, Jim

Hi Jim,

I am truly sorry for the delay on this one. I will prioritize this case going foreward. Could you please provide the schematics?

Bets regards

Kristoffer

Hello Kristoffer,

That sound great, however our client considers the schematics to be confidential. How do you suggest I get them to you?

Thanks, Jim