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TAS5715 Initializing PBTL

Other Parts Discussed in Thread: TAS5715

Hi All,

I want to Initialize the TAS5715 for PBTL Mode.

Is there any initialize procedure?

Note:

1.  I can comunicate the over I²C correctly with the AMP

2. I can measure the output PWM 

3. I can measure the Input I²S Signal

My procedure is as follows:

- Oscillator Trim Register to 0x00

- wait for 250ms

- Master Volume to 0x30 (0dB)

- Shutdowngroup Register to 0x3A

- IC Delay Registers to BD Mode: 0x10 to 0xB8, 0x11 to 0x60, 0x12 to 0xA0, 0x13 to 0x48

- Start/Stop period register to 0x48

- Input Mux register to 0x00897772

- DRC & DC Control Register to 0x03

- PWM Output Mux register to 0x01103245

- System Control 2 Register to 0x00

This procedure is not wroking, So pleas help.

Thanks in advance and best regards,

Daniel

  • Hi, Daniel,

    Welcome to e2e, and thanks for your interest in our products.

    Do you have pin 8 tied high for PBTL mode?

    -d2

  • Hi Don,

    first of all thank you for your fast reply.

    Yes, the pin is tied high. Reset and PDN also.

    Is there a need for to choose BD mode for PBTL?

    However, I tried both modes and failed.

    Do you have any ohter Ideas whats wrong?

    Thanks,


    Daniel

  • Hi Daniel,

    What is the switching frequency of the output PWM? If the input clocks are valid, this should be 8*Fs (where Fs is LRCLK rate).

    Please check the error register (0x02) for any error's. (Note, this register should be cleared by writing x00 before the read-back).

    If the PWM's are switching fine, and no error's are reported, try updating the register 0x25 to (01-00-22-45).

    -Ravi

  • Hi Ravi,

    Many thanks for your post.

    First of all i can say that i fix this problem.

    I figure out that I hoodwinked by the poor documentation.

    I used datasheet: SLOS645 –AUGUST 2010.

    On page 23: Clock, Autodetection, and PLL

    "The clock section uses MCLK or the internal oscillator clock

    (when MCLK is unstable, out of range, or absent) to produce the

    internal clock (DCLK) running at 512 times the PWM switching frequency."

    For my reason that implied that i dont need a MCLK.

    That is wrong!

    By the way...

    - The PWM frequency was 352800Hz by FS = 44100Hz.

    - It seems that the chip produce the PWM without MCLK. That is the next thing!

    - Somebody ( I )  could missinterpret that all is good.

    - The Error register was allways 0x00.

    Now I Use the SCLK also for MCLK.

    In one configuration is MCLK == SCLK == (64*FS)

    The result of all is,

    1. ) that I misanderstand the documentation

    2.) that my initializing sequence works correct.

    Thanks anyway for your good support!

    PS, could somebody initiate a documentation update?

    Daniel