Hi,
I'm trying to evaluate the TLV320DAC3120 chip on a custom breadboard. I'm having issues trying to enable the PLL clock to generate a BCLK and WCLK.
Here's my settings:
Master clock is given on MCLK pin (12 MHz)
BCLK (1.536 MHz) and WCLK (48 kHz) are configured as an OUTPUT
The PLL example configuration on the datasheet says that I should have the following configuration when PLL_CLKIN=12 MHz with a fs=48 kHz
PLP=1 PLLR=1 PLLJ=7 PLLD=1680
MDAC=7 NDAC=2 DOSR=128
CODEC_CLK_IN = PLL_CLK
Register settings:
REGISTER PAGE 0
Reg 4 -> 0x3; // PLL_CLKIN=MCLK & CODEC_CLKIN=PLL_CLK
Reg 5 -> 0x91 = (0x1 << 7) | (0x1 << 4) | 0x1; // PLL ON, P=1, R=1
Reg 6 -> 0x7; // PLL J
Reg 7 -> 0x6; // PLL D-VAL MSB
Reg 8 -> 0x90; // PLL D-VAL LSB
Reg 11 -> 0x82; // NDAC POWER ON; NDAC=2
Reg 12 -> 0x87; // MDAC POWER ON; MDAC=0x7
Reg 13 -> 0x0; DOSR_VAL MSB
Reg 14 -> 0x80; DOSR_VAL LSB
Reg 27 -> 0xC; // I2S; word len=16bits; BCLK output; WCLK output
Reg 29 -> 0x1; // BDIV_CLKIN = DAC_MOD_CLK
Reg 30 -> 0x84; // BCLK POWER ON; BCLK Divider=4
Reg 63 -> 0x90; // DAC Power ON && DAC Data Path=Left data
Reg 64 -> 0x0; // DAC NOT muted
REGISTER PAGE 1
Reg 35 -> 0x80; // DAC router to HPOUT driver
Reg 31 -> 0x80; // HPOUT output driver is powered on
Reg 40 -> 0x4; // HP driver is not muted
Is my PLL configuration correct? Could I be missing some other configuration settings?
The BCLK and WCLK pins are always high. Is as though the PLL is not running. If I set the CODEC_CLKIN = MCLK I see the BCLK and WCLK pins toggling.
Thanks in advance,
Ronald
