AIC3262 Firmware for Android

Hi Sangly,

In cases where the codec acts as I2S master, it is important that  the clock tree be correctly configured to obtain the sample rate you expect to play at.  Unfortunately, given the complexity of the PLL on the AIC3262, we cannot derive this tree at run time in the driver code.  To be power efficient, the clock tree configuration also needs to take into account the process flow being run by the miniDSP or the chosen PRB mode.  

The applications reference guide has suggestions for commonly used master clock frequencies.  If what you are using in you system is different, please let us know and we can make suggestions.  Once you design your clock tree settings, you need to specify this in a cfg file and link it to your firmware <mode> via a <pll> tag in your cfd file. The firmware is generated by running mkcfw on the cfd file.  More details about the firmware creation process are available in the documentation found inside the firmware tools package:

 http://e2e.ti.com/cfs-file.ashx/__key/telligent-evolution-components-attachments/00-64-00-00-00-26-61-69/mkcfw_5F00_r6.10fix6_5F00_130516.zip

Regards,

hari

Hi Mr.Hari

       Currently i'm using 12.5MHz for MCLK from W23 jumper on AIC3262 EVM. But my android firmware's PLL configured for 38MHz that's why i can't hear clear output in speaker i heard very slow music. 

      Now i need to configure the firmware to 12MHz then only i can get the clear sound. But the fact is first time i'm working on AIC3262 and its PLL tree. So i guess its take some time to understand the *.cfg and PLL tree and then changes in firmware. 

      Is there any sample *.cfg for AIC3262 for MCLK=12Mhz, please share with me.

Thanks,

Sangly.

Hi Arbona

 I modified the pll_48khz.acx for sampling frequency 48kHz and I built it. While playing the audio from android its bit faster.

Then I’ve modified the pll_48kHz.acx for sampling frequency 44.1kHz and input values are mentioned below. While I’m playing the audio its playing fine but I can feel the speed of audio is  somewhat better than previous one but not correct speed. 

                Audio is come up with some noise it’s not like audio from USB from PC. What are the other parameters to be change for perfect audio. But while playing in USB BCLK is around 3MHz but while playing from android its 1.5MHz is this the reason for noise ?

 Fs:44.1Khz

MCLK(MHz):12 (Using W23 jumper in AIC232EVM kit)

PLL_CLKIN_DIV:1  PLLP:1 PLLR:1 PLLJ:7 PLLD:560 MADC:3 NADC:5 AOSR:128 MDAC:3 NDAC:5 DOSR:128 

                               Here I’ve attached the modified pll_48kHz.acx please find it and correct me if any.  

#------------------------------
# DAC/ADC CLOCK CONFIG
#------------------------------
# MCLK is 38.4MHz
# PLL_CLK = r*j.D/p = 1*5.1200/2 = 98.304 MHz 
# P=2, R=1 : XPPP RRRR
#android
#PLL_CLK = r*j.D/p = 1*5.1200/2 = 98.304 MHz 
# P=1, R=1 : XPPP RRRR
sreg[PLL_PR_POW] =  0b.0010001;
# J=5 :XXJJ JJJJ
# J=7 :XXJJ JJJJ
sreg[PLL_J] =  0b..000111;
# D= 1200. MSB=04 LSB=B0
# D= 1200. MSB=06 LSB=90
sreg[PLL_D_MSB] =  0x08;
sreg[PLL_D_LSB] =  0x48;
# DIV = 1 XVVV VVVV (128,1-127)
sreg[PLL_CKIN_DIV] =  0b.0000001;
# NDAC = 2: XVVV VVVV (128,1-127)
sreg[NDAC_DIV_POW] =  0b.0000101;
# MDAC = 8 : XVVV VVVV (128,1-127)
# MDAC = 7 : XVVV VVVV (128,1-127)
sreg[MDAC_DIV_POW] =  0b.0000011;
# DOSR = 128 DOSRMSB = 0x00 DOSRLSB = 0x80
sreg[DOSR_MSB] =  0x00;
sreg[DOSR_LSB] =  0x80;
# NADC NADC = 2
# NADC NADC = 7-->Android
sreg[NADC_DIV_POW] =  0b.0000101;
# MADC MADC = 48
# MADC MADC = 2 -->Android
sreg[MADC_DIV_POW] =  0b.000011;
# AOSR = 128
sreg[AOSR] =  128;

#------------------------------
# ASI1 CLOCKS
#------------------------------
# ASI1 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01
sreg[ASI1_BCLK_N_CNTL] =  0b......01;
# BCLK N DIVIDER = 4 : XVVV VVVV
sreg[ASI1_BCLK_N] =  0b.0000100;
# WCLK N DIVIDER = 32 : XVVV VVVV
sreg[ASI1_WCLK_N] =  0b.0100000;
# ASI1 BCLK WCLK OUTPUTS : XBBB XWWWW
# BCLK = BCLK DIV OUT
# WCLK = ASI1 WDIV
sreg[ASI1_BWCLK_OUT_CNTL] =  0b.000.010;

#------------------------------
# ASI2 CLOCKS
#------------------------------
# ASI2 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01
sreg[ASI2_BCLK_N_CNTL] =  0b......01;
# BCLK N DIVIDER = 4 : XVVV VVVV
sreg[ASI2_BCLK_N] =  0b.0000100;
# WCLK N DIVIDER = 32 : XVVV VVVV
sreg[ASI2_WCLK_N] =  0b.0100000;
# ASI2 BCLK WCLK OUTPUTS : XBBB XWWWW
# BCLK = ASI2 BDIV
# WCLK = DAC_FS
sreg[ASI2_BWCLK_OUT_CNTL] =  0b.010.000;

#------------------------------
# ASI3 CLOCKS
#------------------------------
# ASI3 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01
sreg[ASI3_BCLK_N_CNTL] =  0b......01;
# BCLK N DIVIDER = 4 : XVVV VVVV
sreg[ASI3_BCLK_N] =  0b.0000100;
# WCLK N DIVIDER = 32 : XVVV VVVV
sreg[ASI3_WCLK_N] =  0b.0100000;
# ASI3 BCLK WCLK OUTPUTS : XBBB XWWWW
# BCLK = ASI3 BDIV
# WCLK = DAC_FS
sreg[ASI3_BWCLK_OUT_CNTL] =  0b.100.000;

Hi,

Note that the decimal points for the clocks are very important for audio. If you are truly working with 12.000 MHz, then the setting I mentioned applies. But if you're working with 12.288MHz, then you should use other values that give you exactly 48ksps or the desired sampling rate. Also, check this document as well: http://www.ti.com/lit/pdf/slaa469.

Regards,

J-

Hi J 

      You are exactly right. due to DB error only i am haring noise when i play high pitch audio. 

I'm using AIC3262EVM-U and for MCLK i'm using SRC1_MCLK from W23 is it 12MHz or 12.288MHz? but my OSC showing 12.5MHz unfortunately my OSC device is not in good condition so can't measure the exact value. 

How can i set the proper decimal points ? Could you share the proper value to be add modify for SRC1_MCLK and for 44.1Khz sampling rate.?