• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 31 subscribers
  • Views 739 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPA6138A2 ground loop question

Andrew Coad
Expert 1625 points
Other Parts Discussed in Thread: TPA6138A2, TPA6132A2

Hi,

A question on how to design a GLB circuit for the TPA6138A2 device.  The application note "Ground loop break circuits and their operation" (SLOA143) provides designs for the TPA6132A2 device and states that "..this circuit may be implemented very easily with Texas Instruments’ TPA6132A2 or several other devices in the TPA613x family.." Does "other devices" include the TPA6138A2?

In the data sheet, are the two GND pins (4 and 10) actually PGND and SGND and, if so, which is which?

Also, the circuit diagram for the TPA6138A2 EVM shows a RC low pass filter on each output (R23,C20 and R22,C19 for right and left channel respectively).  Are these components an overall part of the filter design or are they related to GLB? Should all designs with the TPA6138A2 incorporate similar?

Regards,

ac

  • 0
    TI__Guru**** 189401 points

    Hi, Andrew,

    Unfortunately, the TPA6138A2 has a slightly different architecture, so the concept is not directly applicable.

    As for the RC LPF, it is mainly for EMI and ESD reasons - for keeping EMI in the box (generated by other parts of the circuit) and ESD out, so it's totally optional, up to your own requirements.

    -d2

  • 0 in reply to Don Dapkus
    TI__Genius 13700 points

    Hello Andrew,

    I have been reviewing your design which was sent to me. My thought is that when the ground break resistor is too large the ground current induces a voltage differential between the ground planes that is large enough to cause one of the grounds to float resulting in signals referenced to the floating ground which could over-volt the pins that they connect to.

    The thoughts that I had looking at your schematic would be to place a decoupling capacitor between AVCC and analog ground and PVCC and the digital ground. The pins AVCC & PVCC would be connected only through a ferrite bead which would provide low pass filtering allow for what would hopefully be a smaller ground loop break resistor while keeping the rails together to address the potential of EOS.

    I will keep digging and confer with some of my colleagues on this and other approaches.