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Two problems in AIC3100 experiments

Problem 1: How to read the volume of MIC inputs in AIC3100 

We'd like to read the volume of Mic inputs in AIC3100.

We have tried to use P0/R102-R106 to measure the volume, however, the value of volume is zero.

Problem 2: How many freq. of MCLK? We have not found the freq. of MCLK in datasheet.

Our problem is that Our I2S signal has noise when we use internal MCLK as I2S reference CLK.

p.s. our application is using two AIC3100s  (bidirectional audio transmission).

  • 1: You cannot measure the volume. Those registers are to measure a DC voltage (if you apply a sine-wave, it'll always average out to zero). You will have to confiugure the ADC clocks and power up the ADC for this to work.

    2. MCLK depends on many different variables. If you don't want to use the PLL, you can calculate an appropriate MCLK by multiplying the sampling rate with the oversampling rate (OSR) and the M & N dividers. The limits are listed in Table 5-41.

    What is your sampling rate and available master clock?

  • Dear D. HartI,

    For question 1: Could you suggest me another same series Audio IC which can be supported a function of volume measurement?

    For question 2: We use "internal MCLK with its PLL (our setup is PLL=MCLK)". Can you tell me what is the corrected value of Freq. (or its range) for this work?

    We directly use internal MCLK, which is  provided by AIC3100, so we don't know what is sampling rate and available master clock.

    P.S. In our experimental environment, we use two AIC3100, and to use internal MCLK with its PLL by itself.

  • 1: You can use the AIC3111 and PurePath Studio, which allows you to develop a measurement algorithm of your choice. This part is pin-pin compatible with the AIC3100.

    2: The AIC3100 requires an external clock (it does not have an internal oscillator). You can either supply a clock that is an integer multiple of your sampling rate and oversampling rate or you can use the internal PLL to derive the internal clocks from a non-standard system clock or even the bit clock on the I2S interface.