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TAS5630B Oscillator sync input

Ron Briggs
Prodigy 10 points
Other Parts Discussed in Thread: TAS5630B, LM5122

We are using  the TAS5630B in a new design and the prototype is set to Master mode operation with a measured Oscillator sync output frequency  of ~4.0 MHz. This matches the expected typical electrical characteristics as specified in the data sheet  for the internal  fosc_io+/-.

We are using a TI (LM5122) 50V switcher to supply PVDD and would like to run the TAS5630B in Slave mode driven from a common synchronizing clock oscillator. 

1) What is the relation between OSC_IO input frequency and Fsw (Switching frequency) in slave mode; Is Fsw the same as input OSC clock or do I need supply  an OSC clock that is  x10 the Fsw.

2)  I would like to know if we can drive the oscillator input with a single ended source  at the OSC + input or does it require a differential clock source at OSC+ and OSC-. 

3) What are the frequency limits of OSC+/-  in slave mode

4) Can we use a clock source with  20% spreading capability? How would this affect device performance?

Please clarify, 

Thanks

  • 0
    TI__Mastermind 37045 points

    Hi Ron,

     

    Please follow the DS oscillator spec on page 10. The oscillator needs to be a low jitter type, since jitter directly translates into audio noise. Duty cycle matching of the two phases is important, since mismatch leads to DC offset in a BTL application. Supply should be well matched to DVDD and PCB routing between the oscillator and osc inputs should be done differentially with good shielding.

    For 400KHz operation, the OSC pin freq is 4MHz (0V-3.3V). The OSC_IO input pins should be treated as differential pairs. The OSC inputs are 180 degree out of phase.

     

    reg,

    Paul.

     

  • 0 in reply to user5276421
    Intellectual 385 points

    Hi TI,

    I noticed that you write that dutycycle mismatch of the clock leads to DC offset. 

    We see that the offset increases considerably with high output power. We are using the internal clock and PBTL mode.

    Is there a chance that the DC offset could be reduced if an external and well defined clock was used? Or is the internal clock in the chip itself best under all circumstances?

    Trond Inge Wang 

  • 0 in reply to trond inge wang
    TI__Mastermind 37045 points

    Hi, Trond,

    I don't think it will help. In the master mode, the output DC offset is mainly due to the input offset of the input amp stage.

    Master mode should have the best output offset.

    reg,

    Paul.