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TLV320AIC3104 I2S Bitclock Issue

Leonid Ayzenshtat
Intellectual 275 points

Hello.

We send DC offset to the Codec on the I2S bus which in the analog domain equates to around 50mVdc.

We are having an issue when the bit clock to the codec is lost it seems that the output of the codec gets stuck in the 50mV state.

Is there some sort of register inside of the codec that can be read from to tell the device on the other side of the I2C bus that something is wrong with the I2S?

Is there perhaps some other setting or register in the codec that can be set such that if the Bit Clock is dropped the output of the codec returns 0?

In our configuration we use the Bit clock internally to generate the 12.288MHz MCLK. And we do not have an MCLK line coming to the codec at all.

Thanks for the help.

Leo

  • 0
    TI__Mastermind 28585 points

    Hi Leo,

    Once BCLK stops, the output should drift to its zero point (+/- some offset). Of course if you are driving a hi-z input, it might take some time to bleed off the charge.

    There is really no way for the converter to report the presence of a BCLK so you would probably just want to monitor BCLK directly.