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TAS5630B - slave clock mode

Cscott
Intellectual 310 points


There are a couple of points on slave mode that are not clear to me.

(1) In slave mode it would seem that the clock input should be 10x the PWM frequency. I don't think this is made clear in the data sheet.

(2) I don't think that data sheet specifies the maximum frequency of operation in slave mode. In internal mode the maximum oscillation  frequency is given but that is not necessarily the same as maximum allowable frequency of operation. Why do I ask? I'd like use 420Khz, 5KHz higher than the highest expected oscillator frequency. 

  • 0
    TI__Mastermind 37045 points

    Hi Nick,

    Yes the clock freq should be F_PWMx10. The oscillator needs to be a low jitter type, since jitter directly translates into audio noise. Duty cycle matching of the two phases is important, since mismatch leads to DC offset in a BTL application. Supply should be well matched to DVDD and PCB routing between the oscillator and osc inputs should be done differentially with good shielding.

    For example, 400KHz operation, the OSC pin freq is 4MHz (0V-3.3V). The OSC_IO input pins should be treated as differential pairs. The OSC inputs are 180 degree out of phase.

    Max PWM Freq is 415KHz which correspond to Osc freq of 4.15MHz.

    reg,

    Paul.