TLV320DAC3100 problem on custom board

Please read back page 0 and page 1 after you completed the configuration and post the results (all registers in page 0 and page 1).

Dear Hartl, 

Thanks for the support please find the attached txt file having dump of page-0 and page-1 registers.

Regards

Vivek

=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2013.12.20 20:41:20 =~=~=~=~=~=~=~=~=~=~=~=
i2s cset -f -y 2 0x18 0x00 0x00
root@IHM_VISIO ~$ i2cdump -f -y 2 0x18
No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 00 00 01 66 03 11 07 11 78 00 00 03 05 00 80 80    ..?f????x..??.??
10: 08 00 01 01 80 80 04 00 00 00 01 0c 00 00 01 00    ?.?????...??..?.
20: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00    ....?...........
30: 00 00 00 02 32 12 03 02 02 11 10 00 19 04 00 14    ...?2??????.??.?
40: 00 d4 d4 00 00 38 00 00 80 00 56 22 09 1c 7f ab    .??..8..?.V"????
50: 00 00 80 00 00 00 00 00 7f 00 00 00 00 00 00 00    ..?.....?.......
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 04 00 00 00 00 00 00 00 00 00 00    .....?..........
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
root@IHM_VISIO ~$ i2cdump -f -y 2 0x18set -f -y 2 0x18 0x00 0x00 1
root@IHM_VISIO ~$ i2cset -f -y 2 0x18 0x00 0x01
root@IHM_VISIO ~$ i2cdump -f -y 2 0x18
No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ?...............
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06    ...............?
20: 06 4e 00 44 92 92 92 7f 06 06 1c 00 20 86 00 80    ?N.D???????. ?.?
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
root@IHM_VISIO ~$ 
root@IHM_VISIO ~$ 
root@IHM_VISIO ~$ 

Dear Mr Hartl,

Any feedback on Register Dump, every thing is ok from configuration side or I missed some thing there?

Thanks and Regards

Vivek

I verified your register initialization sequence on a DAC3100 EVM and can play back music through the headphones without any changes to your register settings.

Your beep generator initialization doesn't enable the beep generator for the left channel:

AUDIO BEEP GENERATION:
======================
i2cset -f -y 2 0x18 0x00 0x00
i2cset -f -y 2 0x18 0x47 0x00 // this should be 0x80 to enable the beep.
i2cset -f -y 2 0x18 0x48 0x80
i2cset -f -y 2 0x18 0x49 0x00
i2cset -f -y 2 0x18 0x4A 0x56

i2cset -f -y 2 0x18 0x4B 0x22
i2cset -f -y 2 0x18 0x4C 0x09
i2cset -f -y 2 0x18 0x4D 0x1C
i2cset -f -y 2 0x18 0x4E 0x7F
i2cset -f -y 2 0x18 0x4F 0xAB

Dear Hartl,

Thanks for reviewing my init sequence and register dumps, as my board has only speaker out I am doing below changes in addition to above sequence:

page-0
i2cset -f -y 2 0x18 0x00 0x00
i2cset -f -y 2 0x18 0x3f 0xd4
i2cset -f -y 2 0x18 0x41 0xfd
i2cset -f -y 2 0x18 0x42 0xfd

page-1
i2cset -f -y 2 0x18 0x00 0x01
i2cset -f -y 2 0x18 0x20 0x86
i2cset -f -y 2 0x18 0x26 0xb4

But still I am not getting any beep or audio, just a click sound in speaker when I play music. 

Any comment why still no audio.

Also one more thing when I make DAC as I2S master why I am not able to get any clock from DAC.

Regards,

Vivek

Dear Hartl,

I am able to play audio on DAC now, many thanks for your support. I have 2 issues now with the DAC

1. It plays audio for some time i.e 15 - 20 Secs and then no audio after that, I probed clocks and Data is present on the lines, also if I stop and play again, audio plays normally for again same time. (DAC is I2S slave here)

2. If I make DAC as I2S master I don't get any clocks out from the DAC.

Thanks and Regards

Vivek

1: Please check register 0x2C, page 0 for any fault conditions (shor circuit/overcurrent). Please also check if your power supply can source enough current for the class-D driver (does the DAC stop after a loud audio signal? Does it also stop if you play back at very low volume levels?).

2: What is your internal clock setup when you choose BCLK/WCLK as outputs in I2S master mode?

Dear Hartl,

1. Please find my observation on your inputs as: 

    A). I could able to see val:0x80 on page-0 reg:0x2C which means short circuit

    B). If I reduce volume my playback is fine i.e not stopping

 So is the problem with my power supply to DAC or something else

2. Please find my clock setting for MCLK=12.37 as input and for 48Khz sample:

//PLL_clkin = MCLK,codec_clkin = PLL_CLK
i2cset -f -y 2 0x18 0x04 0x03

//pll power-up P=1, R=1
i2cset -f -y 2 0x18 0x05 0x91

//J=7
i2cset -f -y 2 0x18 0x06 0x07s

//D=4472: D-MSB=0x11 D-LSB=0x78
i2cset -f -y 2 0x18 0x07 0x11
i2cset -f -y 2 0x18 0x08 0x78

//ndac power-up, NDAC=3
i2cset -f -y 2 0x18 0x0b 0x83
//mdac power-up, MDAC=5
i2cset -f -y 2 0x18 0x0c 0x85s

//DOSR = 128, DOSR(9:8) = 0, DOSR(7:0) = 128
i2cset -f -y 2 0x18 0x0d 0x00
i2cset -f -y 2 0x18 0x0e 0x80

Are these values are fine for clock configuration or I Need some more changes

It's difficult to say without having access to the hardware but something causes excess current out of the speaker output pins when it shuts down. Please make sure you do not have a capacitor to GND on the class-D outputs (some designers may add those to filter out high frequencies).

About the clocks: How did you configure master mode? Did you program the BCLK and WCLK directions to set them as outputs? Besides this, how did you configure the BCLK and WCLK sources?

Dear Hartl,

1. Audio Playback problem at high volume

                   Please find attached my schematic for your review

2. About clocks please find my configurations below:

        a. Master Mode, BCLK, WCLK output: Reg: 0x1B Val: 0x0C

        b. BCLK, WCLK sources: Not setting any register for BCLK and WCLK source and divider may be this is the problem.

Thanks and Regards

Vivek

Please program the BCLK output according to Fig. 5-21. You'll have to power up BDIV in P0.0x1E: Set D7 and the appropriate divider value.

By default the source for BDIV is DAC_CLK. If you want to use DAC_MOD_CLK, you'll also have to set D1:0 from P0.0x1D to 01

Dear Hartl,

Please find my updates for the problems I was facing with the DAC.

1. Clocks out issue when DAC is I2S Master: Solved, Thanks a Lot for you inputs
2. Audio Stoping at High Volume: Not solved
        A). We have ordered the TI-EVK for the DAC and Interfaced it to our custom board by bypassing the on-board DAC, with this setup
and our SW we are able to play audio continuosly at high volume without any issue.
        B). We have also eliminated the possible issues related to power by wiring all the power signals from custom PCB to TI-EVK.
        3817.TI_TLV320DAC3100_layout layers.docC). We now suspect the issue may be related to our PCB layout, we need your support in analysing and point the problem in the
attached layout files.

Thanks and Regards
Vivek

I think this was resolved by removing R265 and R266. Please confirm.