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2-layer or 4-layer PCB for TAS5760

Other Parts Discussed in Thread: TAS5760XXEVM

Hello. I'm Japanese FAE of distributor.
Please help me.

TAS5760 is under consideration by my customer.
My customer trying to use TAS5760 under the following conditions.

・2-layer board/4Ω/11W
or
・4-layer board/4Ω/15W

My customer's question is the following.

①Do TAS5760 support this condition ?
(They want to know it before evaluating)

②Do you have maaterial of recommended pattern at above conditions ?
Otherwise, They cannot use TAS5760.

I'm waiting for your reply.

  • Hi, Asano-san,

    The figure on the front page of the data sheet shows that both these conditions should be possible. It was measured on the TAS5760xxEVM, which is a 2-layer EVM. Of course, thermal performance is dependent on proper use of the PowerPAD and good PCB layout practices.

    Let me see if we have a 4-layer design for this part. The 2-layer design can be found in the EVM.

    -d2

  • Hi, Asano-san,

    I didn't see a 4-layer reference design for the TAS5760, but we have published all the info on the EVM which is a 2-layer design.

    -d2

  • Hi Asano-san,

    One further bit of guidance:

    The PVDD voltage plays a part in how much power can be made. When looking at the plot on the front page of the data sheet, you can see that we can do less power at 24V with a 4ohm load than, say, a 12V supply. This is normal and expected since switching losses (and dissipated heat) increase with voltage across the output FETs.

    In looking at this plot, it appears that the 11W should not be an issue at any PVDD, given proper layout and component placement. Although we have no created a 4 layer EVM, prior experience allows us to be confident that 15W x 2 can be achieved on a 4 layer board.

    Please make sure to submit the schematic/layout on this site for review so we can make sure that your customer follows proper thermal pad/layout/routing techniques as was done on the EVM.

    Thanks!

    Cody