CC85xx Extra I2S Delay

I'm also in this very same situation, where the design in question is a set of (wireless) HiFi stereo speakers, and i was hoping to be able to apply the CC85xx to form the wireless link between the left (master) speaker and the right (slave) , and an optional subwoofer as well .
The left speaker needs to be able to drive its dac/amplifier in sync with the (delayed) I2S signals regenerated at the slave right speaker.
from a programming perspective, within the CC85xx it would seem like a trivial task to copy one of the transmitted channels trough a ring memory buffer fifo (2-4kB) via dma and back out though the I2S data output.
Doing so externally adds significant cost and complexity to an otherwise simple and elegant solution, so it really seems like an unfortunate oversight not to have this feature built-in. I would think many designers would have the same requirement. Anytime the transmitter is embedded in a device with its own speaker or able to transmit wired audio to an external device, this will be mandatory.

At the moment its looking like i will have to add an extra MCU with I2S to take care of this, and assessing how badly that will impact the BOM cost and development timeline.

I'm encouraged at least to see that the CC85xx firmware is being updated with new enhanced features on a regular basis, so i am hopeful that this might be considered for inclusion in a future firmware update :)

Also, being able to dynamically switch between USB source and I2S source would be an extremely desirable capability too, i would also hope somehow that gets added in a future release.

Cheers
Frantz

Hi,

Right now,I am attempting the same thing to generate a compensating delay in the master to feed a local DAC.  I have resorted to using a small Lattice FPGA with built in memory for an audio ring buffer. Its a similar cost to an MCU and being an FPGA, is totally deterministic.

Hi Killian,
thanks for sharing your approach -
I'm curious, can you share which specific Lattice part and budgetary cost ?
For comparison, I've tentatively selected a small Cortex M0 MCU from Infineon (XMC1302) that has direct I2S support , 16k RAM and is worth ~ $1 or so in mid-volume quantities. package is TSSOP-16.

Cheers
Frantz

Hi Frantz,

Thanks for your feedback. The ICE40LM2K and ICE40LM4K parts have 80Kbits of RAM which should be sufficient with enough logic to implement a ring buffer and some more.

Their technical challenge is the BGA package that has a pad pitch of 0.4mm and 0.35mm so the PCB design and the manufacturer's pick and place needs to be up to spec to use these packages. Budgetary pricing is $4 for 100 off so is considerably more than your MCU solution.

I have been considering the ICE40HX4K as it has a more manageable TQ144 package with plenty of IO and integrated PLLs and I wanted to consolidate the  glue logic including multiple I2S interfaces and some audio switching. The part comes in at around $5.50 which starts to look expensive if you are only looking for an I2S delay function. I think for a simple I2S delay, your MCU solution looks very cost effective.

Regards,

Killian

Hi Killian,

Thanks for the info - i had thought about using a small FPGA or CPLD for audio routing as well - in your case it makes total sense to bring in the delay function in there as well -
for me i decided to keep it simple for this first iteration and make do only with the built-in I2S routing functions of the PCM9211, which i'm using for audio inputs - not as flexible as i'd like, and it makes the connections more convoluted than necessary, but in the interest of time-to-market it will have to suffice.. If the product takes off i'll probably use an FPGA for rev 2.

Cheers

Frantz