• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 30 subscribers
  • Views 565 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPA3110D2 pop noise question?

Chen Bogey8
Mastermind 9990 points
Other Parts Discussed in Thread: TPA3110D2

Dear Sir

Good days,

Due to input impedance balance request, may we parallel pin3(LINP) connect Pin12(LINP) and PIN4(LINN) connect PIN11(RINN) for reduce pop noise on TPA3110D2?

                                   Best regards,

                                              Bogey 

  • 0
    TI__Guru**** 189401 points

    Hi, Bogey,

    What, exactly, are you trying to do? Are you running it in PBTL?

    -d2

  • 0 in reply to Don Dapkus
    Mastermind 9990 points

    Hi D2

    May we have another qestion, from Datasheet Figure 37, if one output speaker is open. does another speaker can normal output?

    Enclosed file circuit may you also have some suggestion for us?

    8103.TPA3110D2PWR.pdf

                                                                Best regards,

                                                                                    Bogey

  • 0 in reply to Chen Bogey8
    TI__Mastermind 37045 points

    Hi Bogey,

    For the unused (open) channel, I would suggest load them with 10K resistors after the LC filter.

    reg,

    Paul.

  • 0
    TI__Mastermind 37045 points

    Hi, Bogey,

    Yes, minimizing the input impedance imbalance is to reduce false trigger the DC protection function that may cause the amplifier to shut down. Therefore, the impedance seen at the positive input (LINP) should be as close to the negative input (LINN) as possible. To minimize pop, unmute the amp only after the audio source is charged up to the bias voltage and stable (no glitches).

    When the device is power on, there is a delay of about 14mS for charging up the input voltage to the (pos and neg) internal bias voltage level before the PWM output starts switching. With same impedance at both input, the offset voltage is minimized during this 14mS charge up.

    reg,

    Paul Chen

    Applications Engineer

    Dallas TX