Hello everyone,
I am trying to build a PWM processor around TAS5010 and DIR9001, which uses to clock the system. However Valid_L and Valid_R goes to low and I read 3.3 V in PWM output. I set M_S (0), DBSPD (1) and MCLK_OUT(0), RESET(1), LRCK from 96 kHz, I am using 24.576 MHz crystal with DIR9001 to provide master clock to TAS5010 (MCLK_IN). The values for PLL loop filter components are as same as in the evaluation board. However, PWM OUTUPS show 3.3V and valid_L and R are in error state. In the design is it possible to connect AVSS and DVSS directly ground?. Would that be the cause for the problem?. Your comment is highly appreciated.
Thanks!
Dave