Hi,
On a new design, I have to synchronize the DIT of multiple SRC4392.
For this, I connect BLS of SRC4392 chips together. One BLS will be set as an output and the others as inputs. All SRC4392 DIT are driven by PORT A. All PORT A are driven by the same clock signals, only data signals differ.
My problem is that the datasheet specifies that BLS must be in synch with SYNC signal but SYNC is an output only.
My question : Is my configuration ok ?
Best regards,
Nicolas
