I have a software processor running on an FPGA connected to a TI AIC23 audio codec through a daughtercard. The audio codec is in master mode and generating the lrcin/blck signals that I need to grab data. Since there are no libraries to interface the AIC chip to the FPGA, I'm writing my own.
For reference I am using a DE2i-150 FPGA dev board running a NIOS II software processor and using a Terasic AD/DA data conversion daughtercard with a TI AIC23 chip on it.
My question is for receiving ADC data running the chip in master mode, is the correct way to collect data to trigger an interrupt on the lrcin/lrcout pin to show that there is data ready, then activate an interrupt on the bclk rising edge to show that the data bit is ready. Then collect 16 bits and convert that to an analog value? Let me know if that explanation isn't very clear.
I'm basically trying to follow the I2S diagram in the datasheet to write my library using interrupts that trigger on the lrcin/lrcout and bclk pins.
