Hello,
we have some problems with the adc fine volume control (Page0/Register 82) together with the adc coarse volume control (Page 0/Register 83 and 84) in the TLV320ADC3101. We use the following configuration:
if (src == AUDIO_SRC_LINE)
{
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 0, 0x00); // Select Page 0
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 1, 0x01); // Reset
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 61, 0x00); // ADC Processing Block=1
if (main_Config.AClk == AUDIO_CLK_0) // 18MHz
{
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 4, 0x00); // CODEC_CLKIN = MCLK
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 18, 0x82); // NADC=2, NADC Clock power up
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 19, 0x82); // MADC=2, MADC Clock power up
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 20, 0x60); // AOSR=96
}
if (main_Config.AClk == AUDIO_CLK_1) //49 MHz
{
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 4, 0x03); // CODEC_CLKIN = PLL_CLK
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 5, 0b10110001); // P = 3, R = 1
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 6, 0x05); // J = 5
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 7, 0x18); // D = 6250
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 8, 0x6A); //
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 18, 0x8A); // 82 NADC=10, NADC Clock power up
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 19, 0x82); // 82 MADC=2, MADC Clock power up
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 27, 0x2C); // 2C ADC IF=I2S, Word Length=24Bit, BCLK=Output, WCLK=Output
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 20, 0x60); // 60 AOSR=96
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 22, 0x04); // ADC IADC
}
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 26, 0x81); // 90 CLKOUT Devider M power up
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 25, 0x00); // 00 MCLK
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 38, 0x02); // 02 I2S Control Register
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 30, 0x84); // 84 BCLK Power up N Devider
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 29, 0b00000110); // ADC Interface Control 2, BCLK and WCLK active
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 61, 0x01); // ADC Processing Block=1
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 81, 0b11000000); // ADC Left/Right power up
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 82, 0x00); // ADC Left/Right not muted
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 83, 0b00010011); // ADC Left Volume control
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 84, 0b00010011); // ADC Right Volume control
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 0, 0x01); // Select Page 1
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 52, 0xFC); // LCH_SEL1 = 0dB
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 55, 0xFC); // RCH_SEL1 = 0dB
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 59, 0x00); // Left PGA not muted
xtwi_WriteReg(&TwiMaster, SLAVE_ADDRESS_ADC3101, 60, 0x00); // Right PGA not muted
}
We put a signal on the line input and check the output amplitude while changing the adc coarse and fine volume control registers (Page0/Registers 82,83,84). The fine volume control doesn't work as expected. We can see a change in the output amplitude when changing from 0 to -0.4db. When using the others settings (-0.3db, -0.2db, -0.1db, 0db) there is absolutely no change in the output amplitude.
Is there any precondition in order to be able to use the fine volume control?
Thanks in advance and have a nice day
Marc
