+3.3V CMOS <=> unbalanced AES3 driver / receiver needed.

Hi, Sergio,

Take a look at the DIX4192, I think it meets your requirements.

-d2

Hello, Don!

Thank You for Your answer.
I know this part, but I need a much more simpler and cheaper solution, maybe based on some parts from TI SNxx families of devices.

Hi, Sergei,

Unfortunately, the SNxx devices are general-purpose catalog devices, and I don't know anything about them (I only work on our audio devices).

Perhaps someone in the community can chime in on their experience of using standard logic parts instead of customize audio devices to accomplish this?

-d2

Hello, Don!
After searching the web, I found out, that  "+3.3V CMOS <=> balanced AES3 driver / receiver" can be done by TI DS89C21.
What is Your opinion on this solution?

Hi, Sergei,

I am not sure if that can be used if you need to certify your system to be compatible with AES3.

-d2

Hello, Don!

Please then comment on this information from DIX4192 datasheet ( page 31 ):

"The SN75ALS191 dual line driver is especially useful in applications where simultaneous 75 Ohm and 110 Ohm line interfaces are required." ( page 31 ).

This is almost exactly what I need: AESOUT ( +3.3V CMOS ) is converted to 75 Ohm interface ( unbalanced AES ) with the help of SN75ALS191 which is a RS422 driver.

In my case +3.3V CMOS output is, of course ,coming not from DIX4192, but from a FPGA.

Is there anything else has to be added or modified to the above Fig.34 to be fully compatible with AES3 balanced ( 110 Ohm ) and AES3 unbalanced ( 75 Ohm )?  Maybe it has to be AC-coupled or any RC network should be to limit the output slew rate or maybe smth else?

On unbalanced output you can connect resistor voltage divider to match voltage 0.5V and impedance 75R. Also it is a good idea to have capacitor 10-100nF to suppress DC voltage. Also you can use pulse transformer (S22083, PE-65612 or DA102C) for galvanic isolation of signal.

On balanced outputs you can connect resistor voltage dividers to match voltage 2-7V. Or maybe serial resistors 55R are enough for right output impedance 110R. Also you can use two capacitors 10-100nF to suppress DC voltage and also pulse transformer for galvanic isolation of output.

Hello, Pavel!

So, You are suggesting to treat the outputs of SN75ALS191 as TX outputs of DIX4192 and use the schematics at Fig.30 and 31 of DIX4192 datasheet for 110 Ohm balanced and 75 Ohm unbalanced interfaces respectively?

Yes, exactly. I have good experience with RS422 transceiver and this schematics. Only difference is that I used SN75176B because I had +5V TTL logic.

Hi Pavel,

sounds like your already having fun! AES3 is electrically identical to RS422. However, I also read that your trying to find a 3V3 I2S-AES3 converter, as well as TX?

DIT4192 was originally specified for a 5V rail, however, we have some research that shows that it'll do up to 96kHz content from a 3V3 rail.

Regards

Dafydd

Also, for the AES3 to CMOS reciever circuit, have a look at the DIR9001 Datasheet and Evaluation board. I believe there's also a similar circuit on the DRV602 evaluation board.