I am having trouble coming up with the correct PLL/clock settings to achieve a 48Khz sample rate, 16 bit samples, using a 12.288 MHz clock using an AIC 3204 on my custom board. Can someone give me a hand with the correct values for these parameters? Here is what I have so far, but the BCLK and WCLK are slightly high:
/* PLL and Clocks config and Power Up */
AIC3204_rset( 0, 0 );
AIC3204_rset( 27, 0x0d ); // BCLK and WCLK is set as output from AIC3204(Master)
AIC3204_rset( 28, 0x00 ); // Data offset = 0
AIC3204_rset( 4, 3 ); // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
AIC3204_rset( 6, 7 ); // PLL setting: J=7
AIC3204_rset( 7, 0x06 ); // PLL setting: HI_BYTE(D)
AIC3204_rset( 8, 0x90 ); // PLL setting: LO_BYTE(D)
AIC3204_rset( 30, 0x88 ); // For 32 bit clocks per frame in Master mode ONLY
// BCLK=DAC_CLK/N =(12,228,000/8) = 1.536MHz = 32*fs
AIC3204_rset( 5, 0x91 ); // PLL setting: Power up PLL, P=1 and R=1__delay_cycles(20000);
AIC3204_rset( 13, 0 ); // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversampling
AIC3204_rset( 14, 0x80 ); // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
AIC3204_rset( 20, 0x80 ); // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
AIC3204_rset( 11, 0x87 ); // Power up NDAC and set NDAC value to 7
AIC3204_rset( 12, 0x82 ); // Power up MDAC and set MDAC value to 2
AIC3204_rset( 18, 0x87 ); // Power up NADC and set NADC value to 7
AIC3204_rset( 19, 0x82 ); // Power up MADC and set MADC value to 2
