TAS5760M Detection Method of Clock Errors

Kato-san,

As discussed in our meeting page 34 table1 of the TAS5760M d/s summarizes the clock error handling.

During a clock error event e.g. SCLK stop then start, the output takes ~1us to shutdown and 1ms to resume. It takes ~35ms for the output to resume to the volume level before the clock error occurred. This time will vary depending on volume level setting as explained in the Digital Boost and Volume Control section on page 32 of d/s.

Kato-san,

We discussed this in our face to face meeting last month. It's a set of counters and if count varies from one cycle to the next  on any of the counters it triggers a clock error. The table in the datasheet is very clear on the conditions that will trigger the clock error.

1. Non-Supported MCLK to LRCK and/or SCLK to LRCK Ratio (1fs to detect error and 40fs to clear error) 

2. Non-Supported MCLK or LRCK rate (~1us to detect error and ~1ms to clear error)

3. MCLK, SCLK or LRCK has stopped (~1us to detect error and ~1ms to clear error)