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AIC3104 DAC output switching

Donald Reay
Expert 1545 points

Hi,

I have a problem with an AIC3104 concerning apparent signal 'leakage' from right input to left output.

If I select DAC3 output path then I see no problem, but if I select DAC1 output path then a small fraction of the right channel input appears added to the left output.

I am running a program that writes zero value sample data to DIN on both channels. At the same time I have analogue inputs present on both channels (sinusoids of different frequencies so that I can distinguish the sources.

If I replace this

    I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 41, 0x50); // DAC_L3, DAC_R3 paths

with this

    I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 41, 0x00); // DAC_L1, DAC_R1 paths

    I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 81, 0x00 ); // PGA_L not connected to LEFT LOPM
    I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 84, 0x00 ); // PGA_R not connected to LEFT LOPM
    I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 85, 0x00 ); // DAC_R1 not connected to LEFT LOPM
    I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 82, 0x80 ); // DAC_L1 IS connected to LEFT LOPM

    I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 88, 0x00 );
    I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 89, 0x00 );

I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 91, 0x00 );    

I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 92, 0x80 );

I go from seeing zero output on both channels (no problem using DAC3) to seeing a sinusoid of the frequency applied to right channel input, on the left channel output (problem using DAC1!)

Instead of writing zero values via DIN I can pass the input signal via DOUT to DIN and then (using DAC1) I see the expected output sinusoids on left and right channels BUT added to the left output is a fraction of the right input signal.

I see this effect even if the frequency of the right input signal is greater than half the sampling frequency used by the DAC and ADC.

I never seem to get left channel input appearing on right channel output.

Anyone else seen this, or have any suggestions?


Donald

  • 0
    TI__Guru**** 189401 points

    Hi, Donald,

    That is very strange. i suspect it's an issue with the way you're programming the registers. Can you double-check your register settings?

    -d2

  • 0 in reply to Don Dapkus
    Expert 1545 points

    Hi Don,

    Thanks for replying.

    Does my register-writing function I2CRegWrite() work correctly?

    Can't be 100% sure but in general I am getting the AI3104 to behave as I intend - changes in values written to registers have the anticipated effects on routing, gain settings, etc. So I am pretty confident of that mechanism.

    Am I writing to the registers in the wrong order, or writing incorrect values, or relying on default values that are not
    correctly implemented?

    I suspect that this is the problem.

    Since my last post I have found that I can get the problem even if using DAC3 - it depends what you write to registers 81,82,84,85,88,89,91,92.
     
    My test setup is that I am inputting sinusoids of around 500mVp-p magnitude and of different frequencies to LINE1LP and LINE1RP. A microcontroller is running a program that copies DOUT to DIN. Using DAC3 I see the two sinusoids on LEFTLOP and RIGHTLOP as expected. When I make the configuration changes I see the expected sinusoid output on RIGHTLOP but the LEFTLOP output comprises the expected sinusoid (from  LINE1LP) plus the sinusoid from LINE1RP (at about 10% magnitude compared to output on RIGHTLOP).

    The configuration below appears to work for me. Writing 0x50 to register 41 selects the DAC3 option, in which case the writes to  registers 81,82,84,85,88,89,91,92 should be irrelevant? (all default 0x00).

    However, I can cause my problem (even using DAC3) simply by writing 0x80 to register 82. DAC_L1 into LEFTLOPM Volume control.

    Writing 0x80 to register 16 (mute right ADC PGA) has no effect on the LEFT output - it still contains an element of right input (but of course means no right channel signal).

    Leaving register 22 to its default (LINE1RP not connected to ADC PGA) does eliminate the problem (but of course means no right channel signal).

    One thing that I do not understand is why it is necessary to set bit 0 in registers 86 and 93 - the datasheet lists these bits as read only.

    So is the problem in the LEFTLOPM volume control mixer? Is it letting through some PGA_R when it shouldn't, i.e. when regs 81,84,85 are zero but when reg 82 (DAC_L1)
    is enabled?

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 0, 0x00); // select registers in page 0
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 1, 0x80); // reset codec

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 2, 0xAA); // fsref divisors
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 3, 0x10); // PLL disable Q = 2 -> fsref 48kHz
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 7, 0x0A); // datapath setup and fsref 48kHz

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 8, 0xC0); // codec is BCLK and WCLK master

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 9, 0xC0); // left justified mode 16 bit per channel
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 10, 0x00); // no data offset

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 15, 0x00); // left input PGA gain 0dB
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 16, 0x00); // right input PGA gain 0dB

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 19, 0x04); //
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 22, 0x04); //


    // configure output

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 81, 0x00 );
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 84, 0x00 ); // PGA_R to LEFT LOPM mixer
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 85, 0x00 );
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 91, 0x00 );
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 88, 0x00 );
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 89, 0x00 );

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 82, 0x00 ); // DAC_L1 to LEFT LOPM mixer
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 92, 0x00 );

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 41, 0x50); // DAC_L3, DAC_R3 to LINE OUT


      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 86, 0x09 ); // WHY DOES BIT 0 HAVE TO BE SET?
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 93, 0x09 );

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 43, 0x00); // Left DAC Digital Volume Mute=OFF, Gain=0dB
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 44, 0x00); // Right DAC Digital Volume Mute=OFF, Gain=0dB

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 37, 0xc0); // power up left and right DACs and HPLCOM=SingleEnd

      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 101, 0x01); //
      I2CRegWrite(I2C1_BASE, AIC3104_SLAVE_ADDRESS, 102, 0x00); //

  • 0 in reply to Donald Reay
    TI__Guru**** 189401 points

    Hi, Donald,

    Sorry for the delay. I've asked my colleague to look thru your register writes and see if he can spot the problem. Give him a day or two to check it out.

    -d2

  • 0 in reply to Don Dapkus
    Expert 1545 points

    Hi Don,

    Did your colleague have any suggestions regarding the register writes?


    Regards,


    Donald