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About the parallel connection of PCM1804.

Satoshi
Guru 19645 points
Other Parts Discussed in Thread: PCM1804, PCM1804S

When parallel connection of PCM1804 is carried out, is there any way to synchronize the frequency of ADC?

I think that it is realizable by the method of connecting DSD (15～17pin) of PMC1804's, like an application note(attached,2-page).

7612.slaa508.pdf
 
If my idea has mistaken, please let me know.

Moreover, if PCM1804 can't synchronize, please let me know about other device which matched (synchronize).

 

Best regards,

Satoshi

  • 0
    TI__Guru**** 189401 points

    Hi, Satoshi,

    I don't understand what you mean by "parallel connection." Can you explain more about what you are trying to do?

    I don't think that app note may be applicable, it is for a different family of parts.

    -d2

  • 0 in reply to Don Dapkus
    Guru 19645 points

    Dear Don-san

    Thank you for reply.

    The customer's specification was checked.
    ---------------------------------
    ・A customer's hope is synchronized operation, sampling to the same timing, and a data output.

    ・I checked that there was a function required for PCM1804.

    ・If a device is set as SlaveMode, and the same clock is supplied to SCLKI, LRCK, and BCK, synchronized operation.

    ※A Buffer course is recommended.
    ※An each phase is required for a clock. (Designs in the same distance)
    ---------------------------------

    ⇒Customer want the data explaining the above-mentioned operation.

    Using the information on the 22page of the datasheet, since it is small, if there are more detailed data, please let me know.
     
    Especially, customer wants to know sampling timing .
    If the sampling timing of SlaveMode is a ramp(or fall) time of LRCK, they can be convinced, but is it right?

     

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    Guru 19645 points

    How is a situation about the question asked the other day?

    Is there what should otherwise be checked with a customer?

  • 0 in reply to Satoshi
    TI__Guru**** 189401 points

    Hi, Satoshi,

    Sorry for the delay, let me see what I can find.

    -d2

  • 0
    TI__Guru 62006 points

    The app note is for a device with a PLL that uses the PLL to generate the internal clocks of the master device and the bit clock for the parallel slave devices. This is not applicable to the PCM1804 because the PCM1804 does not have a PLL and therefore requires an exact and accurate master clock.

    If you apply the same master clock to all PCM1804s in your system and you use the same reset signal, the PCM1804s will be synchronized and you can use them in parallel.

  • 0 in reply to Dominik Hartl11
    Guru 19645 points

    Do you have the data about this function in Internal?

    If you don't have, since I answers that there is no information, please let me know.

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    TI__Guru 62006 points

    I don't have specific data for this use case but if you use the same MCLK for all PCM1804s, they will operate in sync.

  • 0 in reply to Dominik Hartl11
    Guru 19645 points

    Dear D. Hartl-san

    Thank you for reply.

    Since interface is serial 1-bit, sampling timing of the slave mode was performed in falling or the standup of LRCK, and when the timing of LRCK synchronized, I thought that sampling timing also synchronized.

    Isn't operation of hope carried out if MCLK(s) differ?

    Moreover, is MCLK mean SCKI of PCM1804? (Or LRCK or BCK)

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    Guru 19645 points

    I was pushed by the customer.

    I wrote idea the other day, is it right?

  • 0 in reply to Satoshi
    TI__Guru 62006 points

    MCLK=SCKI. Same thing. I just used a more common term for the same thing. If the master clock is the same between the PCM1804s and the reset timing is the same, they will run in sync.

    >If the sampling timing of SlaveMode is a ramp(or fall) time of LRCK, they can be convinced, but is it right?

    You need to synchronize the parts with the same master clock (SCKI) because this is what drives the part internally. This is an oversampling converter meaning it samples at a much higher rate than the sampling rate.  For example, if you choose single rate and you want to use a 48kHz sampling rate in slave mode, the oversampling rate is either 256, 384, 512 or 768, depending on the applied master clock (SCKI). So the part samples the input at the resulting oversampling frequency of either 12.288 MHz, 18.432 MHz, 24.576 MHz or 36.864 MHz. The exact phase of the LRCK in slave mode is not critical and will not affect the "sampling timing of SlaveMode" as you wrote in your question. You must make sure that the host supplies the LRCK at the correct rate but the actual sampling is timed by SCKI.

    You should also use the same word clock (LRCK) and ideally the same bit clock (BCK) for all PCM1804s.