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PCM5102A - questions

WCL
Prodigy 10 points
Other Parts Discussed in Thread: PCM5102A, PCM5102

I have several questions about the PCM5102A:

  1. The chip offers 2 options for the clock input, as stated in the datasheet. Either a 4-wire I2S input (with a system clock) can be used, or the 3-wire "System Clock PLL" mode can be used. The second option does not require a clock signal from the source, and relies on the chip's internal PLL. Which method of connection should be used for maximum sound quality and low jitter?
  2. When setting options on the chip (such as with the DEMP and FLT pins), is it okay to directly connect the pin to ground for a "low" connection, and directly to the 3.3V supply for a "high" connection? If not, what value resistors should be used (3.3V mode).
  3. I have noticed that the schematic of the PCM5102 EVM differs slightly from the recommended schematic on the datasheet. The EVM schematic contains what I believe are decoupling electrolyctic caps and ceramic caps on the power supply, while the datasheet only has ceramics.

    EVM
    Datasheet


    Should I follow the datasheet or EVM implementation?

Thanks.

  • 0
    TI__Guru**** 189401 points

    Hi, WCL,

    thanks for your interest in our product!

    Sound quality should be the same using external clock or pll. 

    It is ok to tie those pins directly to supply or ground. 

    On the Evm schematic, the electrolytic caps are labeled, "DNP" which stands for Do Not Populate. So, if you were to buy an Evm, you would find those components are not actually on the board. so, I believe the ds and evm align.

    let me know if you have any further questions. 

    D2

  • 0
    Expert 1720 points

    Hi,

    1. System clock PLL has some limitation like not supporting higher frequencies than 96kHz. If I understand correctly. Also some combination of system clock and sample frequencies are not supported. If you have high quality jitter-free System clock, it will be probably better to use them.

    2. I connected pins directly to the ground and supply without any troubles.

    3. It already answered by Don.

    Best regards, Pavel.

  • 0 in reply to Pavel Ruzicka
    TI__Guru**** 189401 points

    Hi, Pavel,

    Thanks for spending the time to add your comments! It's nice to see others contribute their real-world experiences to e2e!

    -d2

  • 0 in reply to Don Dapkus
    Prodigy 210 points

    Hi,

    I used PCM5102 with CM6631A USB-I2S converter, and have found the problem without MCLK at 44/48 sample rate.

    At Fs=88/96/176/192, this converter generates the regular BCLK, which is 64Fs.

    PCM5102 - works fine.

    But at Fs=44/48, this converter produces BCLK as 128Fs. PCM5102 without MCLK does not works at all.

    With MCLK - everithing is OK.

    --

  • 0 in reply to Alto
    Expert 1720 points

    Hi,

    this is probably OK, because PCM5102A support only BCK 32FS and 64FS in PLL mode. Details are in datasheet on page 12. In my opinion it will be better to use SCK (MCLK) from your USB->I2S converter.

    Best regards,

    Pavel

  • 0 in reply to Pavel Ruzicka
    Prodigy 210 points

    Hi,

    sure, I must  use MCLK from the converter, in order 44|48 works.

    But I'm also want to put galvanic isolation between the converter and DAC , and I'm afraid that with ISO76xx MCLK's jitter will be high.

  • 0 in reply to Don Dapkus
    Prodigy 10 points
    I do not want to start a new topic, so I will ask here.
    And where you can learn from a power line running modulators of the DAC?
    It is necessary to choose the right linear regulators on the level of noise