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TLV320AIC3254 Codec Clocks/Interfaces setttings

Niroshan Karunaratne
Prodigy 145 points
Other Parts Discussed in Thread: TLV320AIC3254EVM-K, TLV320AIC3254

Hello

I am using the TLV320AIC3254EVM-K Evaluation Board. 

When I route the audio signal form IN1 through MAL/MAR to line outputs (without using DSP) from the AIC3254 CS software, providing a sine wave at the input produces a near perfect sine wave at the output. 

Non-Distorted sine wave when analog input is routed to analog output by passing DSP processor   

However when I route IN1 through DSP_A_DSP_D (using PurePath as shown in the above image) to line output, Providing a 5000Hz sine wave signal to the input produces a distorted waveform at the output.

And the distortion of the waveform (shape of the wave) changers when the parameters in the Digital settings -> Clocks/Interfaces panel of the  AIC3254 CS software (PLL parameters R,J,D,P and  NADC, MADC, etc) are changed.

Distorted sine wave when routed through DSP processor 

My application requires the use of the DSP.

I tried to use R,J,D,P parameters generated by PLL Calculator in the AIC3254 but still can not get  the required output (5000Hz sine waveform).

How ever low frequencies (bello 1000Hz) are produced correctly at the output.

Could you please let me know how to config the Clock interface parameters correctly.

Thank you in advance,

  • 0
    TI__Mastermind 46195 points

    I will get back to you soon.

    Regards,

    J-

  • 0
    TI__Mastermind 46195 points

    Hi Niroshan,

    Most audio codecs employ sigma delta modulation in their DACs. To determine if the noise observed on your plot is normal or not, you would need to measure with a spectrum analyzer (see http://www.ti.com/lit/pdf/slaa313), or implement a sharp low pass filter at 20kHz. In other words, performance (noise and distortion) shown in the datasheet is bounded within a speciifed bandwidth.

    Regards,

    J-

  • 0 in reply to J-
    Prodigy 145 points

    Hello J Arbona

    Thank you for the response.

    I think I found the solution. I was using the AIC3254App8x4x framework. In the Framework Help I found that Matching Components were Dec4xIn, Int8xOut, DSP_D_DSP_A DSP_A_DSP_D. In my PPS project I was using Int2xOut as the output instead of Int8xOut. Changing to the proper output seams to solve the problem. 

    However I am facing another issue.

    I am using BCLK as PLL_CLKIN which is generated by a I2S interface of a Bluetooth module. But this BCLK clock seams to be jittered. Could the PLL of the TLV320AIC3254 Codec handle a jittered input.

    Thank you

    Niroshan 

  • 0 in reply to Niroshan Karunaratne
    TI__Mastermind 46195 points

    Hi Niroshan,

    The converters are designed to handle up to 100ps cycle-cycle jitter for their master clock. The PLL output jitter is also 100ps, so higher jitter into the PLL could work. I suggest testing the clock with the device EVM to see the response on an FFT. Jitter usually manifests itself as 'skirts' which become worse as frequency is increased. You can try 1kHz 0dBFS input into both ADCs and DACs and increase up to 20kHz to see if skirts show up at the bottom of the fundamental in the FFT.

    Regards,

    J-