LM49352 registers clarification

Hi, Ivan,

0x00h.  Please see figure 57 in the datasheet.  Port clock is the bit clock for associated I2S port.  You can generate the chips internal clock from various clock sources. (ie MCLK pin, port1 bitclock.) Also the MC clock controls the power management block of the LM49352 and sets the turn on time of the analog output stages. The PMC clock should operate around 300kHz for optimum tradeoff between turn-on time and click/pop performance.

0x21h Again please see figure 57.  %ADC or ADC_CLK_DIV sets the divider into the ADC.  The ADC should be running at 2 * OSR * Fsamplerate.  Depending on clock to the ADC 0x20h[6:4] you will need to setup the correct divider into the ADC for correct operation.  The dividers allow ratios of 1 to 128 in 0.5(half cycle) steps.

0x31h same as 0x21 but for the DAC.  You need to set the clock rate of the DAC correctly.

0x45h  Always the ports to use the decimator for sample rate conversion.  Needed for OSR signals. See http://en.wikipedia.org/wiki/Decimation_(signal_processing)

-Matt

Hi Matt

Could I check with you on a couple of registers.

I2S port

0x524h      -   What is a SYNTH_Demon

0x00h        -   Bits 4,5,6 , what does the _ovr bits do?

Ivan

0x52h is Synth_Denom  (Denominator).  You can select 128 or 125.  Then in Synth_Num you can choose the numerator to get ratios like 96/128 or 96/125 .....  This is when you use the audio ports and want to generate the master clock (CLK_Master) it allows flexibility in the clocking output.  Please look at pgs 52-56 in the data sheet for the other fields that are needed to configure the parts to generate the clock when configured as master.  To configure the port as master you do this in 0x50h bit 3 Clock_MS.

For 0x00h OVR this is override.  It allows the digital ports and clocks to be used when the part is in shutdown allowing for example the digitial mixer to be used when the analog blocks are shutdown.  Please see page 32 of the datasheet for information.