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TLV320AIC3100 Config the codec when ADC/DAC has different sample rate.

Xin Liu Alex
Prodigy 10 points

Hi

I would like to config the codec so that the ADC/DAC has different sample rate. (e.g ADC is 32000Hz and DAC is 8000hz) . However the problem is once we configure the DAC/ADC mod clock to get different sample rate, the WCLK in I2S interface ( should equal to sample rate) always match the lower clock in ADC/DAC. In our case, it will stay on 8000 hz instead of 32000hz. In the datasheet of audio codec, we know how to configure BCLK of I2S by choose the it source from ADC mod clock or DAC mod clock. However there's no notes or comments on how to configure the WCLK when ADC/DAC has different sample rate. All the application notes we can find seems assume the ADC/DAC has same sample rate or the WCLK is from outside input.

So the question in general is  how would we configure ADC/DAC clock and I2S interface clocks when ADC/DAC has different sample rate?  

thank you

  • 0
    TI__Intellectual 2710 points

    Hi, Alex,

    I will help on your post. I will  update it later today.

     

    Thanks,

    Flora Wang

     

  • 0
    TI__Intellectual 2710 points

    Hi,Alex,

    I believe you have already had a good unstanding about the clock in our Codec. very good!

    1.If you use different sampling rates for the ADC and the DAC, you must also use two separate Frame Sync (=WCLK) signals, one for the ADC and one for the DAC. If you use the same FS (WCLK) for both the ADC and DAC then both will effectively convert at the same rate because you'll feed/read data at the same sample rate.

    2.AIC3100 has Primary and Secondary Audio Interface,so that  you can configure WCLK out = DAC_FS and GPIO 1= ADC_FS. Check page 78.

    3.The bit clock can be shared by both ADC and DAC but it must be running fast enough to allow for the faster sampling rate(32khz).

     

    Thanks,

    Flora Wang