I have a design where I have a low frequency MCLK (812 kHz) with some phase jitter. The PLL then produces all clock signals for 48 kHz sample rate. There is noise in digital output that depends very much on phase jitter in MCLK signal.
The analog input is a waveform at 6 kHz that is synchronous with WCLK.
1) Are there any special limits for phase jitter/clock frequency for MCLK when using PLL?
2) Would a RC oscillator be better than the PLL for CODEC_CLKIN?
3) Would a Crystal oscillator be better than the PLL for CODEC_CLKIN?
The waveform is a stable baseline with a pulse, 50 microseconds long, rise & fall time 5 microseconds. For 8 consecutive samples, I get 6 points at baseline and 2 at pulse.
However, output digital data shows the step and the baseline with stable values, but the baseline is not flat.
When I adjust the pulse position in the 8 sample interval (I can adjust it in BCLK steps) and/or the pulse width, the baseline values will change to new values, but I have not yet found any values that will make the baseline flat.
4) Can this be caused by the digital filter?
I have tried to make a program with PurePath program that just sends data through without any processing. It was just input with 4 decimator and output, connected together. I have not tested that yet.
5) Is it correct that such a program should be several hundred bytes of code?
Kurt Mirdell
