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aic3204 and Register 27

I'm encountering a bit of a head-scratcher on the aic3204. The following code puts data on the DOUT pin until I try to set Register 27 D7-D6 to DSP mode (01).

I2S(00), RJF(10) and LJF(11) all put data on DOUT, and BCLK and WCLK appear normal in all 4 modes.

This code is not derived from the CS program, so it's entirely possible some registers are being loaded out of sequence. Being that DSP is the mode I'd like to use, it's a little inconvenient.  :)

What am I missing?

# clockin = 16.384MHz
# page 0

30 00 00

30 01 01   # page 0, reset

30 0B 81

30 0C 81   # ndac, mdac

30 0D 00

30 0E 40   # dosr

30 12 82

30 13 82   # nadc, madc

30 1B 7C   # <-- herein lies the problem? FC, BC and 3C all work

30 1C 00

30 1D 00   # not sure if I need these anymore, but...

30 1E 84   # bclk N

30 3C 08   $ prb_p8

30 14 40   # aosr

30 34 1C   # pin 32 is WCLK

30 35 12   # may or may not be necessary

30 3D 0D   # prb_r13

# page 1

30 00 01

30 01 08   # disable weak avdd/dvdd

30 02 A1   # vdd's = 1.77

30 7B 01   # vref 40ms

30 09 0C   # LOL/LOR

30 12 3A

30 13 3A   # set gain

30 0E 08

30 0F 08   # set routing

30 0A 08   # common mode

30 34 C0

30 36 C0

30 37 C0   # input routing

30 39 F0

# page 0, unmute, bring online

30 51 C0

30 52 00

30 53 28

30 54 28

30 41 21

30 42 21

30 3F D6

30 40 00

  • Hi, Randy,

    I'm not sure I understand. You're feeding it I2S, and it works fine, then you reconfigure the input clocks for DSP mode, and switch the part to DSP mode, and it doesn't output data?

    -d2

  • Hi Randy,

    On line 68, it looks like you want to switch to Page 0, but the command to switch pagw is not issued...

    Regards,

    J-

  • Oops, my bad. I managed to snip the line that switched to page 0, but it is there.

  • Hi Randy,

    I'd strongly recommend to follow the scripts in AIC3204 software or the ones in the Design and Configuration Guide app note, simply to follow a known working setup. Then it is a matter of setting the audio interface mode to I2S and the offset value according to the host requirements.

    Regards,

    J-

  • I've set the clocks for output to the micro, WCLK on pin 32.  When I set Reg 27 to FC, BC or 3C, I get signal on Dout, which my micro, for now, feeds back to Din. BCLK and WCLK come out normal as per the timing diagrams.

    When I change the value to 7C, I get BCLK and the brief WCLK pulses I see in the DSP timing diagram, but Dout stays low. I wondered if there was another reg setting I was missing.

  • J Arbona said:

    I'd strongly recommend to follow the scripts in AIC3204 software or the ones in the Design and Configuration Guide app note, simply to follow a known working setup. Then it is a matter of setting the audio interface mode to I2S and the offset value according to the host requirements.

    Thanks for replying. I d/l'd the CS software v1.2.1 some time ago, but I never could get it to show me an updated script.  I'd hit Refresh on all the windows, but the Script tab would never change. Now I just use the tooltips to locate registers.

  • Hi Randy,

    You would have to press the record button in the Command Line interface. However, this only records button presses (not refreshes). The actual scripts being sent are found here: C:\Program Files (x86)\Texas Instruments\AIC3254 CS\DATA\EVM\AIC3254\PLAYBACK.

    Regards,

    J-

  • J Arbona said:

    You would have to press the record button in the Command Line interface. However, this only records button presses (not refreshes). The actual scripts being sent are found here: C:\Program Files (x86)\Texas Instruments\AIC3254 CS\DATA\EVM\AIC3254\PLAYBACK.

    I must still be doing something wrong. I found the directory, set up the controls, 'refreshed' each panel, went to the Command Line panel, record, execute,nothing. 'Save Script' creates an empty file. I also tried opening a sample script first, hoping it would update it...

    Just to be clear, I'm not using any kind of dev board with this - will the software only create a script if it detects a USB connection?

  • HI Randy,

    Ah, you do need an EVM to be connected. The TLV320AIC3254EVM-U (the AIC3254 is s/w compatible with AIC3204) would be the lowest cost EVM you could use.

    Regards,

    J-

  • That's unfortunate. It would be a much more useful tool if it generated scripts with or without an evm.

    I don't suppose anyone has a working script that uses the DSP mode? I can't help thinking I'm missing one silly bit - somewhere, in some un-guessed register.


    So close...

  • Hi Randy,

    Settings for DSP mode should exactly as I2S, except that you have to set the mode to DSP and set the offset to correspond to the apps processor. Make sure the DSP mode timing diagram matches.

    Regards,

    J-

  • J Arbona said:

    Settings for DSP mode should exactly as I2S, except that you have to set the mode to DSP and set the offset to correspond to the apps processor. Make sure the DSP mode timing diagram matches.


    That's why it's a head-scratcher; if I make r27 bits 7:6=01, my Dout disappears. any other value for those two bits (I2S, RJF, LJF) gives me the normal outputs for those modes. I guess I'll have to solder up another board to see if it's a problem with this individual device. I'll post the results.

    BTW, I really appreciate you walking through this with me. Thanks much.

  • Nope, different pcb, all new parts, same problem.

  • Well, after 2 weeks of trying various permutations&combinations, I'm no closer to a solution.

    Does anyone have a script fragment, or a link, anything that they know works with the 3204 in DSP mode? Otherwise I have to go looking for another device.

  • Randy,

    Please follow the script below. It assumes a 11.2896MHz MCLK, 44.1kHz sampling. It outputs BCLK = 6.144MHz and WCLK = 44.1kHz. The internal analog LDO is powered.

    ###############################################
    # Software Reset
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # Initialize the device through software reset
    w 30 01 01
    #
    ###############################################
    
    
    
    ###############################################
    # Clock and Interface Settings
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # PLL_clkin = MCLK, codec_clkin = PLL_CLK,
    # PLL on, P=1, R=1, J=8, D=0000
    w 30 04 03 91 08 00 00
    #
    # NDAC = 2, MDAC = 8, dividers powered on
    w 30 0b 82 88
    #
    # DOSR = 128
    w 30 0D 00 80
    #
    # NADC = 2, MADC = 8, dividers powered on
    w 30 12 82 88
    #
    # AOSR = 128
    w 30 14 80
    #
    # BCLK and WCLK are outputs, DSP Mode
    w 30 1B 4C
    #
    # Data Offset = 1
    w 30 1C 01
    #
    # BDIV_CLKIN = DAC_MOD_CLK
    w 30 1D 01
    #
    # N divider = 1, powered
    w 30 1E 81
    #
    ###############################################
    
    
    
    ###############################################
    # Configure Power Supplies
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Power AVDD LDO
    w 30 02 09
    #
    # Disable weak AVDD in presence of external
    # AVDD supply
    w 30 01 08
    #
    # Enable Master Analog Power Control
    w 30 02 01
    #
    # Set the input power-up time to 3.1ms (for ADC)
    w 30 47 32
    #
    # Set the REF charging time to 40ms
    w 30 7b 01
    #
    ###############################################
    
    
    
    ###############################################
    # Configure Processing Blocks
    ###############################################
    #
    # Select Page 0
    w 30 00 00
    #
    # PRB_P2 and PRB_R2 selected
    w 30 3C 02 02
    #
    ###############################################
    
    
    
    ###############################################
    # Configure ADC Channel
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # Route IN1L to LEFT_P with 20K input impedance
    w 30 34 80
    #
    # Route CM1L to LEFT_M with 20K input impedance
    w 30 36 80
    #
    # Route IN1R to RIGHT_P with 20K input impedance
    w 30 37 80
    #
    # Route CM1R to RIGHT_M with 20K input impedance
    w 30 39 80
    #
    # Unmute Left MICPGA, Gain selection of 6dB to
    # make channel gain 0dB, since 20K input
    # impedance is used single ended
    w 30 3b 0c
    #
    # Unmute Right MICPGA, Gain selection of 6dB to
    # make channel gain 0dB, since 20K input
    # impedance is used single ended
    w 30 3c 0c
    #
    # Select Page 0
    w 30 00 00
    #
    # Power up LADC/RADC
    w 30 51 c0
    #
    # Unmute LADC/RADC
    w 30 52 00
    #
    ###############################################
    
    
    
    ###############################################
    # Configure DAC Channel
    ###############################################
    #
    # Select Page 1
    w 30 00 01
    #
    # De-pop: 5 time constants, 6k resistance
    w 30 14 25
    #
    # Route LDAC/RDAC to HPL/HPR
    w 30 0c 08 08
    #
    # Power up HPL/HPR
    w 30 09 30
    #
    # Unmute HPL/HPR driver, 0dB Gain
    w 30 10 00 00
    #
    # Select Page 0
    w 30 00 00
    #
    # DAC => 0dB
    w 30 41 00 00
    #
    # Power up LDAC/RDAC
    w 30 3f d6
    #
    # Unmute LDAC/RDAC
    w 30 40 00
    #
    ###############################################
    

    Regards,

    J-

  • It works!

    I'll have to tweak it a bit, but at least I have a working baseline to go back to.


    Thankyouthankyouthankyou!  :)

  • Thanks for the follow-up. Glad you got it working!