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AIC3106 ADC phase

Christopher Hicks
Prodigy 40 points

I am considering using four AIC3106 CODECs in the same system (and driven by the same clocks) to sample 8 audio channels simultaneously and independently.

Is there any way to ensure that the samples on all four CODECs are taken in phase with each other (ie all 8 channels sampled at the same instant)? On many CODECs the sampling instants have a fixed phase relationship with the edges of the IIS WCLK, but the data sheet for the AIC3106 does not say anything about this, so far as I can see.

Christopher Hicks

==

  • 0
    TI__Mastermind 28585 points

    Hi Christopher,

    Here is an app note that was written for the ADC3101 which has a similar sampling mechanism. Although the registers are slightly different, this technique will work for the AIC3106 as well:

    http://www.ti.com/lit/an/slaa508/slaa508.pdf

    Let me know if you have any specific questions.

    dave

  • 0 in reply to Converter Apps
    Prodigy 40 points

    Thanks for the reply.

    We had our boards made using the AIC3106 but now we come to scrutinise the app note (for the 3101) and the data sheet for the 3106 in detail, we find that they are actually rather different in this area.  So we tried to use the principles in the 3101 app note and adapt them to the clock structure in the 3106, but so far without complete success.

    In fact, our application does not use the PLL at all since we operate at a fixed sample rate (16kHz) and have chosen an MCLK source at a convenient multiple of this. We are feeding this clock to the CODECs from a CPLD, so our idea was to disable the clock feed, set all the clock chains up in all the CODECs, and then enable the clock in the CPLD simultaneously to all CODECs.

    During our CODEC startup code, we write 0 to bit D0 of register 101 to set the CODEC_CLKIN. If we do this write before enabling the clocks then the DAC section of the 3106 fails to start correctly (or at all?), but the ADC seems to start fine. If we do the write after enabling the clocks, then both the ADC and DAC sections seem to start up correctly, but if I have understood the app note correctly, I will not be able to guarantee the ADC phase in this case - enabling the clock simultaneously to all CODECs has to be the last step.

    We also believe that there is a misprint on the 3106 data sheet here: the Sitara EVM uses a 3106, and the starter-ware example code writes 1 to bit D0 to select the PLL as the clock source, and seems to work as expected. Our code writes 0 to select the other clock chain and also seems to work (as long as the clocks are running when we do it). This is an inversion of the information on the data sheet.

    This seems to be a simple misprint, but since it is in an area where we are having a little difficulty getting the part to work as expected, I just wonder if we have missed or overlooked something. Any thoughts?

    Christopher Hicks

  • 0 in reply to Christopher Hicks
    Prodigy 40 points

    Oops. I think I may have spoken too soon.  With fresh eyes this morning I have noticed that one of the calls in setting up the CODEC was a CodecRegBitClr( ... 0x01) and not a CodecRegWrite( ... 0x01). The effect of these is rather different!

    I now do not suspect a misprint on the data sheet - sorry - and I do seem to be able to set up all the clock routing and dividers without the clock running, so perhaps a solution is in sight.

    CH
    ==

  • 0 in reply to Christopher Hicks
    TI__Guru**** 189401 points

    Hi, Christopher,

    Great! Thanks for letting us know.

    -d2