We’re working on a project that uses a Bluegiga WT32 Bluetooth module as an A2DP SINK and sends the audio data out of the WT32’s I2S interface to a TI TAS5727 amplifier chip. To assist with development we’re using a WT32 Dev Kit along with a TI TAS5727EVM Dev Kit.
- Currently, the I2S header pins on the WT32 dev kit are connected directly to the I2S header pins of our amplifier’s dev kit. The WT32 will act as a master and send data to the amplifier.
- Both dev kits share a common ground.
- We can configure the amplifier chip on the TAS5727EVM and play I2S audio that the amplifier receives from another component on the TAS5727EVM dev kit. That component is a TI PCM1808PW. However, when we try to send I2S audio to the amplifier from the WT32, we get no sound.
- We can successfully pair with, and connect to the WT32 Bluetooth module using a mobile phone.
- We can successfully play Bluetooth audio from the WT32 dev kit using a line out on the dev kit.
- We’re fairly certain that the reason we can’t get the amplifier to play I2S audio from the WT32 has to do with the configuration of the I2S interface. Currently, that is the only link in the chain that we can’t seem to get working. The TAS5727 amplifier chip reports various clock errors (register 0x02) when we try to send I2S audio from the WT32 to the amplifier. We’re reading the clock errors over I2C and see values of 0xB0 and occasionally 0xC0 depending on how the WT32 is configured. 0xB0 indicates a error on MCLK, SCLK, and LRCLK. 0xC0 indicates an error on MCLK and a PLL autolock error.
Here are some of our configuration settings on the WT32:
WT32 is freshly flashed with iWRAP 5.0.2 build 764 (Generic).
Over a serial connection, we set the following:
SET BT CLASS 240428
SET PROFILE A2DP SINK
SET PROFILE AVRCP CONTROLLER
SET CONTROL CODEC SBC JOINT_STEREO 44100 0
SET CONTROL AUDIO INTERNAL I2S
RESET
From here, we can pair and connect with the WT32 and begin sending audio from a mobile phone. We can clearly observe the digital audio signals on the amplifiers SCLK, LRCLK, and SDIN pins using an oscilloscope.
- LRCLK runs at the expected 44.1 KHz as reported by our o-scope (f_s = 44.1 KHz).
- The TAS5727 requires both an MCLK and SCLK. Since the WT32 doesn’t provide an MCLK, we are feeding both the MCLK and the SCLK inputs of the TAS5727 with the PCM_CLK output of the WT32. For the TAS5727, this means that both the MCLK and the SCLK inputs need to be running at 64 * f_s (or 2.822 MHz). This is because the maximum rate for SCLK on the TAS5727 is 64 * f_s and the minimum rate of MCLK on the TAS5727 is 64 * f_s. The frequency 64 * f_s is the only overlapping value that is valid for both MCLK and SCLK.
- QUESTIONS:
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Given our current configuration, is there anything that jumps out as obviously wrong?
What might cause the TAS5727 to continually report clock errors even though we can see the clocks are behaving as expected via our o-scope?
Does anyone have any experience debugging I2S interfaces and con maybe provide some tips, suggestions, debugging ideas, or even long-shot guesses at what the problem might be?
Any comments would be greatly appreciated. I feel like we’ve tried just about everything with no luck.
Thanks for reading, and hopefully for your comments.