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I am using the ADC PCM4202 and I have a problem with the THD+N:
THD +N rise up at high level of input signal. See the next figure (Blue: THD+N; Red: Input level):
I can’t get the -105 dB of THD+N that specifies datasheet.
My board has every decoupling capacitors like demo board although my input analog circuit is different from the demo board. See next figure:
The ADC is setting in slave mode, HPFD disable, dual rate with clock auto-detection and fSCKI = 256 fs, fs= 96 Khz.
How could I improve the THD+N in this conditions? Thanks very much.
Hi Daniel,
I will be looking into this today and I hope to get beck with you early this week.
Justin
Hi Daniel,
Poor capacitors are a common cause for increased THD (Y5V is generally not recommended), another could be the voltage rating of the capacitors. We usually recommend twice the voltage you expect the capacitor to experience. Jitter in crystals can also be a source of THD or any other source on non-linearities.
Have you also seen this result using the EVM?
Justin
Hi Justin,
We have used capacitor with at least twice the voltage. I have obtained these results in our board.
We have obtained the same effect In three prototypes. I think this problem is caused by some capacitor, but I do not know points may be more sensitive to THD in the ADC. I'll try to change the capacitors.
Thanks.