We are using TLV320AIC3106 codec in our new FXO module. We have two codecs on one TDM bus. Codecs are connected to BlackFin DSP (BF592) via SPI and serial port. Serial audio interface on codecs set to DSP mode. Master clock is delivered from BCLK pin of serial interface. MCLK pins are left float. BCLK frequency is 2048 MHz, so we need to use PLL with P=1, R=1, D=0, J=48. DAC and ADC sample rate is 8kHz. For test purpose we send from DSP G.711 0dBm sequence - 1kHz sin wave.
The first problem we encountered is related to value in Register 102. Previously we setup this register to value 0x22 (CLKDIV_IN from MCLK, PLLCLK_IN from BCLK, default PLL N) and there was no signal from DAC output. Output signal appeared when we wrote to this register value 0xA2 (CLKDIV_IN from BCLK). It seems that the CLKDIV_IN signal is used internally even when the PLL is enabled. Is it truth?
The second problem is value of bit D1 from Register 86 (LEFT LOP/M Volume Control Status). After LOP/M is powered up and unmuted ( "1" was wrote to bits D0 and D3 in Register 86) this bit is always read as "1" - "Not all gains is applied yet". DAC output and volume control in Register 43 works normally.
Our initialization sequence is:
(10) <- 0x20 /* Set timeslot , only for second codec */
(9) <- 0x20 /* 3-state output in unused timeslots */
(102) <- 0xA2 /* Master clock sources from BCLK */
(3) <- 0x91 /* PLL enable, Q=2 (default), P=1 */
(11) <- 0x01 /* PLL R=1 */
(4) <- 0x30 /*PLL J = 48 */
(2) <- 0xAA /* Sample Rate 1/6 = 8kHz */
(7) <- 0xA /* Left DAC from left, Right DAC from Right */
(41) <-0x50 /* DACs R3 DataPath */
(37) <- 0x80 /* Left DAC powered up */
(19) <- 0x84 /* Left ADC powered up, Line1L differential */
(15) <- 0x80 /* Left ADC unmute */
(43) <- 0x00 /* Left DAC unmute */
(86) <- 0x09 /* LOP/M power up and unmute */
All other registers are left unchanged.
Are there any requirements for order of initialization Serial Interface, Clock and PLL ?
Best regards, Alexander Smirnov.
