Hello,
From the datasheet page 16:
"In Slave mode, the BCK and LRCK signals are inputs, with the clocks being generated by a master timing source, such as a DSP serial port, PLL clock synthesizer, or a crystal oscillator/divider circuit. The BCK rate is typically equal to 128fS in Single Rate sampling mode, and 64fS in Dual or Quad Rate sampling modes. Although other BCK clock rates are possible, they are not recommended as a result if potential clock phase sensitivity issues, which can degrade the dynamic performance of the PCM4202. The LRCK clock must be operated at fS, the output sampling rate."
Could you please explain why it is not recommennded to run BCK at 64Fs when in Single Rate mode? I have not seen any problems with this so far.
Thank you for your help,
David
