Clocking and synchronizing delta-sigma converters

Marek Petrinec

Other Parts Discussed in Thread: PCM4220, PCM1794A

Hello!

I am working on project where i need to know few things so this question is for TI engineers.

So my first question is how are clocking delta-sigma converters in PCM4220. I mean when is the analogue signal converted to digital. Is it synchronized with falling or rising edge of LRCLK? If yes witch edge is it and does the jitter in LRCLK turns into error during conversion? Are both channels converted simultaneously?

My second question is if are both channels in PCM1794A converted simultaneously or separated with edges LRCLK? If are converted simultaneously on which edge of LRCLK are converted?

I need surely information's and are very valuable for me because i am working on my own start-up which is engaged in new type of audio device. Are able to provide me full clock tree of these two ICs? If not please tell me at least the information's i need.

Please be free to contact me on mail marek.petrinec@petrinec.technology

Best regards

over 10 years ago

0 Pavel Ruzicka over 10 years ago

Expert 1720 points

Hi Marek,

I am not employer, but I will try answer to you.
Both channels are converted simultaneously, but data are sent first for left-channel and next for right-channel.
About LRCK. It depend on data format. Most universal is I2S data format in which LRCK falling down after whole frame is sent.
In left-justified format LRCK rising-up.

Answer for your second question for PCM1794A is same like for ADC. Channels are converted simultaneously, if I remember.
Edge of LRCK depends on selected data format. I suggest to use I2S. Details about timing are in datasheet.

In datasheet is specified "group delay" which specify delay of ADC processing and depend on selected filter.

Best regards,

Pavel

0 Marek Petrinec over 10 years ago in reply to Pavel Ruzicka

Prodigy 50 points

Hi Pavel!

Thanks but i know data formats of PCM but this question is how is PCM Clock connected with delta-sigma modulator :) I need to know when the converting starts. If it is derived from edge of LRCLK or not. This is the most interesting thing i need to know. :)

0 Pavel Ruzicka over 10 years ago in reply to Marek Petrinec

Expert 1720 points

Hi Marek, I don't know if somebody can answer to your qustion, but you can built ADC by yourself and measure it with oscilloscope. :-)
Pavel

0 Marek Petrinec over 10 years ago in reply to Pavel Ruzicka

Prodigy 50 points

I know but i need to know if calculate with Cirrus Logic or Texas Instruments ICs. I would prefer TI so i hope engineers will know answers :)

0 Justin Bohr over 10 years ago in reply to Marek Petrinec

TI__Mastermind 27990 points

Hi Marek,

I apologize for the delay, I will look into this for you and get back to you when I have some information.

Justin

0 Marek Petrinec2 over 10 years ago in reply to Justin Bohr

Prodigy 90 points

Hello Justin!

Any news?

0 Justin Bohr over 10 years ago in reply to Marek Petrinec2

TI__Mastermind 27990 points

Hi Marek,

The internal sampling of the analog signal is oversampling at a much faster rate than LRCK and and average of those samples is what is pushed to the next stage. I have sent contacted the design team to find out when this average is captured to be sent to the next stage and will get back to you when they have responded.

Justin

0 Marek Petrinec2 over 10 years ago in reply to Justin Bohr

Prodigy 90 points

Hi Justin!

I know this but the sampling must be started with something. It is probably edge of LRCLK but i need to know it exactly. And which one of it is it.
I will wait for answer.

Best regards
Marek

0 Marek Petrinec2 over 10 years ago in reply to Marek Petrinec2

Prodigy 90 points

Justin i dont need to know when is average pushed on output, I need to know when conversion starts. Probubly conversion duration is 1/fs. Is it right?

0 Justin Bohr over 10 years ago in reply to Marek Petrinec2

TI__Mastermind 27990 points

Hi Marek,

I have sent a query to the Design team and will let you know when I get more information.

Justin

0 Marek Petrinec over 10 years ago in reply to Justin Bohr

Prodigy 50 points

Hi Justin. Iam waiting altought month for answer and still nothing. Whats wrong?

0 Justin Bohr over 10 years ago in reply to Marek Petrinec

TI__Mastermind 27990 points

Hi Marek,

Our design team has been very busy recently, I have escalated these questions and hope to have an answer soon. I apologize for the delay.

Justin

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Clocking and synchronizing delta-sigma converters