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TLV320AIC23B output problem

Other Parts Discussed in Thread: TLV320AIC23B, TLV320DAC23

Hello,

I'm working with the stereo codec TLV320AIC23B and I can´t manage to get an audio signal at the output. What I get is a DC level.

I have configured the device in DAC mode using I2C. It's working as slave. The MCLK frequency is 12.288 MHz, the BCLK frequency is 1.536 MHz and the Fs is 48 KHz. I'm transmitting 16-bit samples with I2S. I have checked all signals in the device pins, clock frequencies and data are correct. Vdd is 3.3 V and at the output I get 1.6 V.

The values I have written in the registers are the following:

LLICVC (0x00): 0x97

RLICVC (0x01): 0x97

LCHVC (0x02): 0x1DB

RCHVC (0x03): 0x1DB

AAPC (0x004: 0x12

DAPC (0x05): 0x01

PDC (0x06): 0x67

DAIF (0x07): 0x02

SRC (0x08): 0x00

DIA (0x09): 0x01

RR (0x0F): 0x00

Any ideas?

Thanks in advance

  • Hi Javier

    By looking at your register configuration, I have a question:

    Why is the PDC (power down control) register set to 0x67. According to these bits, clock and the oscillator both are off. You are using the device in slave mode, so I think clock bit should be on.

  • Hello Vikas,

    I disabled these bits because according to the application note 'Dynamic Behavior of the TLV320DAC23 and the TLV320AIC23B' if OSC is disabled, MCLK still functions. And regarding to the CLK bit, it powers off the CLKOUT pin because we don't need it.

    Anyway, I also tried with PDC = 0x07 (CLK and OSC options enabled) and I got exactly the same at the output.

    Thank you for your replay.

    Regards

  • Hi Javier

    In that case I have some more questions to ask you:

    1. Is it the EVM you are testing on? May be the part is in problem? can you try a new EVM?

    2. Can you please send me the schematic as it seems the DAC is not functioning as the output is at common mode?

  • Hello Vikas,

    We have placed the TLV320AIC23B in our own audio board. I have attached the schematic of the circuit, where capacitors S12 y S13 are not mounted for testing.

    I have one question related to the frequency of BCLK. At the end of page 24 of  the datasheet it is said that when the codec is configured in normal mode (Sample Rate Control register), BCLK = MCLK/4 at all sample rates except 88.2 kHz and 96 kHz.

    We are generating a BCLK of 1.536 MHz = MCLK/8, we use this signal as the I2S clock (Fs = 48 KHz, oversampling = 256 * Fs, MCLK = 256 * 48 KHz = 12.288 MHz). So I don't understand the note of page 24.

  • Hi Javier

    That is interesting. You have everything good on your schematic also.Also the note in the datasheet BCLK=MCLK/4 is only applicable for Master mode when the codec generates BCLK, in slave mode we supply BCLK so your settings are fine.

    So the next thing to try will be:

    1. Using SRC register (address 0001000) bit D7, can you please probe on CLKOUT pin to check if I2C is fine i.e. the registers are being written. CLKOUT should be equal to MCLK if D7 bit is written as 0 and will be MCLK/2 if D7 bit is 1. If you don't see any CLKOUT, that means I2C bus is in problem.

    2. Can you please pop the part that you are using and try soldering a new part. It may be that the current part is damaged.

    3. If all this does not makes a difference, can you please send us the timing diagrams of I2C and I2S bus?

  • Hello Vikas,

    Today, I finally managed to fix this problem. As you said everyrhing was ok, and the problem was in the PCM samples. The codec was only playing the first samples from a wav file, and these values were too slow, so the ripple in the DC level at the output was extremely low. I was testing it within a loop, and trying with another file I've been able to hear the audio of the first samples. Now I have to make same changes in the program to bufferize the file and send all parts to the codec, but I don't have it very clear yet.

    Thank you very much for your help.

    Best regards