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AIC3254 BCLK jitter implications in voice mono

LostElectron
Prodigy 180 points

I am going to use a AIC3254 in slave mode controlling from FPGA:

MCLK,BCLK,WCLK.

BCLK output from FPGA should have low jitter: 100ps cycle to cycle rms or less. 

1/

What are the implications if the constraint below is not met.

2/

do you know if that constraint can be "released" for voice application (8Khz mono)

and if yes how much this can be ?

 

  • 0
    TI__Mastermind 46195 points

    Hello,

    The device is designed to withstand 100ps of jitter as you mentioned. If the jitter is a bit higher than that, you will start seeing skirts in FFTs which gets worse with input frequency as well as distortion components. If it is much more than that you will start getting audible noise artifacts.

    Regards,

    J-