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TLV320DAC3100 clock setting

Atsushi Yamauchi
Genius 4810 points
Other Parts Discussed in Thread: TLV320DAC3100

I would like to confirm clock setting of TLV320DAC3100.

Our customer uses TLV320DAC3100 as I2C slave and WCLK/BCLK are input.

1. How should they set MCLK frequency? Are there any provisions?

     Or can they set any frequencys <50MHz?

     If if is OK for < 50MHz, should they set  1MHz < the frequency <50MHz for delay timer?

2. For on-chip PLL, can they use on-chip PLL by only setting "1"" for D7 of Page 0 / Register 11 (0x0B): DAC NDAC_VAL without MCLK?

3. If they can 2., can they set "1" of D7 by I2C without MCLK? Or do they need MCLK?

Best regards,

Atsushi Yamauchi

  • 0
    TI__Intellectual 2295 points

    Hi, Atsushi-san, 

    1.The MCLK divider must be set such a way that the divider output is ~1 MHz for the timers to be closer to the programmed value. see below, the interval timer clock:

    For this, you can set different MCLK divider Page 3 / Register 16 (0x10): Timer Clock MCLK Divider as long as MCLK frequency <50MHz

    2. Yes, the fractional PLL can be used to generate an Internal Master Clock used to produce the processing clocks needed but either the BLCK or GPIO1 should be the PLL input.

    PLLCLKIN can be set up as MCLK or BLCK or GPIO1 for clocking the DAC, refer to page 0 / register 4, bits D3–D2.

    The source reference clock for the codec can be chosen by programming the CODEC_CLKIN value on page 0 / register 4, bits D1–D0: 11 to set the PLL_CLK (generated on-chip). 

    3.The PLL_CLK generates the CODEC_CLKIN for the NDAC. The MCLK is not needed. 

    Thanks, 

    Mohamed 

  • 0 in reply to Mohamed Hellal
    Genius 4810 points

    Dear Mohamed-san,

    Thank you for your reply.

    I would like to confirm the MCLK frequency.

    The divider output is should be set - 1MHz.

    In this case, can they set low frequency for MCLK (<1MHz)?

    I think they can use <1MHz (ex 500kHz, 20kHz and so on), because IC needs <1MHz for PLL.

    Is it correct?

    Best regards,

    Atsushi Yamauchi

  • 0 in reply to Atsushi Yamauchi
    TI__Intellectual 2295 points
    Dear Atsushi-san,

    Yes correct, there is no minimum value condition for the MCLK.

    Best regards,
    Mohamed Hellal