I'm looking into a strange problem with the AIC3254 codec. I'm using the codec with a differential mono input (on IN1_L and IN1_R) connected to the output of our external microphone preamp. We have a stereo output on LOR/LOL. The DAC/output works fine. The input generally works fine, except for immediately following a hardware reset.
Following a hardware reset, my DSP comes up and programs the codec registers. At this point, the ADC output of the codec is a low-level white noise at a level much lower than we expect. By tapping on the microphone (enough to cause clipping on the input), the level of the microphone signal comes up to the normal expected level. The ADC works normally after this point. A software-initiated reset of the codec does NOT cause the ADC output to revert back to "bad" state.
I'm attaching a WAV file of the codec output (captured using a logic analyzer on the I2S bus, converted to WAV). The initial ~2 seconds of audio are the "bad" state. I tapped on the microphone about 2 seconds into the recording. Following the tap, you can hear the background noise of the room at the level I expect. I tap the microphone again at about 3.5 seconds.
The sequence of codec writes to configure the codec are as follows:
/* Configure AIC3204 */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 1, 0x01 ); // Reset codec
EVM5517_waitusec(10000);
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 1, 0x08 ); // Disable crude AVDD generation from DVDD
AIC3204_rset( 2, 0x01 ); // Enable Analog Blocks and AVDD LDO
AIC3204_rset( 10, 0x40 ); // Set Vcm = 0.75 for AVDD=1.72V
/* PLL and Clocks config and Power Up */
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 27, 0x0d ); // BCLK and WCLK are set as o/p; AIC3204(Master)
AIC3204_rset( 4, 0x00 ); // Clocks - PLL input is MCLK, CODEC_CLKIN is MCLK
AIC3204_rset( 11, 0x83 ); // NDAC = 3, DAC_CLK = CODEC_CLKIN / 3 = 12288kHz / 3 = 4096kHz
AIC3204_rset( 12, 0x82 ); // MDAC = 2, DAC_MOD_CLK = DAC_CLK / 2 = 2048kHz
AIC3204_rset( 13, 0x00 ); // DOSR[9:8] = 0
AIC3204_rset( 14, 0x80 ); // DOSR[7:0] = 128. DAC_FS = DAC_MOD_CLK / 128 = 2048kHz / 128 = 16kHz
AIC3204_rset( 18, 0x83 ); // NADC = 3. ADC_CLK = CODEC_CLKIN / 3 = 12288kHz / 3 = 4096kHz
AIC3204_rset( 19, 0x82 ); // MADC = 2. ADC_MOD_CLK = ADC_CLK / 2 = 2048kHz
AIC3204_rset( 20, 0x80 ); // AOSR = 128. ADC_FS = ADC_MOD_CLK / 128 = 2048kHz / 128 = 16kHz
AIC3204_rset( 29, 0x01 ); // BDIV_CLKIN = DAC_MOD_CLK = 2048MHz
AIC3204_rset( 30, 0x84 ); // BCLK = DAC_MOD_CLK / 4 = 2048kHz / 4 = 512kHz
AIC3204_rset( 60, 0x01 ); // Configure DAC Processing Block PRB_P1 = 1
AIC3204_rset( 61, 0x02 ); // Configure ADC Processing Block PRB_R2 = 2
/* DAC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 14, 0x08 ); // Left Channel DAC reconstruction filter output is routed to LOL
AIC3204_rset( 15, 0x08 ); // Right Channel DAC reconstruction filter output is routed to LOR
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 64, 0x00 ); // L and R DAC not muted, have independent volume control
AIC3204_rset( 65, 0x00 ); // L DAC volume = +0.0dB.
AIC3204_rset( 66, 0x00 ); // R DAC volume = +0.0dB.
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 18, 0x40 ); // LOL driver muted, gain = 0dB
AIC3204_rset( 19, 0x40 ); // LOR driver muted, gain = 0dB
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 63, 0xd4 ); // L and R DAC power up, L DAC is left channel, R DAC is right channel
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 9 , 0x0C ); // Power up LOL and LOR drivers
/* ADC ROUTING and Power Up */
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 51, 0x40 ); // MICBIAS powered on, 1.04V, from AVDD
AIC3204_rset( 55, 0xC0 ); // Right MICPGA+ from IN1R through 40k (-6dB)
AIC3204_rset( 57, 0x30 ); // Right MICPGA- from IN1L through 40k (-6dB)
AIC3204_rset( 58, 0x3c ); // IN2L/R, IN3L/R weakly driven to CM
/* Sample Rate = 16000
* Filter 1 High Pass 2nd Order Variable Q = 0.707, 400 Hz Fc 0.0 dB
*
* BQ: H(z) = (N0 + 2*N1/z + N2/(z2)) / (8388608 - 2*D1/z - D2/(z2))
* Filter Coefficients in format N0, N1, N2, D1, D2
*
* 0x728A48
* 0x8D75B8
* 0x728A48
* 0x71D4A9
* 0x998031
*/
aic3204_cset (7, 0x728A48);
aic3204_cset (8, 0x8D75B8);
aic3204_cset (9, 0x728A48);
aic3204_cset (10, 0x71D4A9);
aic3204_cset (11, 0x998031);
aic3204_cset (39, 0x728A48);
aic3204_cset (40, 0x8D75B8);
aic3204_cset (41, 0x728A48);
aic3204_cset (42, 0x71D4A9);
aic3204_cset (43, 0x998031);
AIC3204_rset( 0, 0x01 ); // Select page 1
AIC3204_rset( 59, 0x00 ); // Left MICPGA gain = 0.0dB
AIC3204_rset( 60, 0x00 ); // Right MICPGA gain = 0.0dB
AIC3204_rset( 0, 0x00 ); // Select page 0
AIC3204_rset( 86, 0x00 ); // Turn off left AGC
AIC3204_rset( 94, 0x00 ); // Turn off right AGC
AIC3204_rset( 81, 0x40 ); // Power on right ADC
AIC3204_rset( 82, 0x88 ); // Mute left and right ADC
Any help that you could provide in helping me understand why the microphone audio doesn't immediately work (without tapping) would be much appreciated.
Thanks.
Randy.
